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IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
MOTOROLA
M68060 USER’S MANUAL
9-9
Figure 9-5. Input Pin Cell (I.Pin)
Figure 9-6. Output Control Cell (IO.Ctl)
FROM
INPUT PIN
CLOCK DR
SHIFT DR
1
1
G1 1
1
G1
MODE
TO
SYSTEM
LOGIC
TO
NEXT
CELL
FROM
LAST
CELL
1D
C1
1D
C1
UPDATE DR
OUTPUT CONTROL
FROM SYSTEM LOGIC
FROM
LAST
CELL
CLOCK DR
SHIFT DR TO NEXT CELL
TO OUTPUT
BUFFER
(1 = DRIVE)
1 = EXTEST
0 = OTHERWISE
1D
C1
1
MUX
1
G1
1
MUX
1
G1
UPDATE DR
1D
C1
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