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Introduction
MOTOROLA
M68060 USER’S MANUAL
1-3
1.1 DIFFERENCES AMONG M68060 FAMILY MEMBERS
Because the functionality of individual M68060 family members are similar, this manual is
organized so that the reader will take the following differences into account while reading
the rest of this manual. Unless otherwise noted, all references to MC68060, with the excep-
tion of the differences outlined below, will apply to the MC68060, MC68LC060, and
MC68EC060. The following paragraphs describe how the MC68LC060 and the
MC68EC060 differ from the MC68060.
1.1.1 MC68LC060
The MC68LC060 is a derivative of the MC68060. The MC68LC060 has the same execution
unit and MMU as the MC68060, but has no FPU. The MC68LC060 is 100% pin compatible
with the MC68060. Disregard all information concerning the FPU when reading this manual.
The following difference exists between the MC68LC060 and the MC68060:
The MC68LC060 does not contain an FPU. When floating-point instructions are
encountered, a floating-point disabled exception is taken.
1.1.2 MC68EC060
The MC68EC060 is a derivative of the MC68060. The MC68EC060 has the same execution
unit as the MC68060, but has no FPU or paged MMU, which embedded control applications
generally do not require. Disregard information concerning the FPU and MMU when reading
this manual. The MC68EC060 is pin compatible with the MC68060. The following differ-
ences exist between the MC68EC060 and the MC68060:
The MC68EC060 does not contain an FPU. When floating-point instructions are
encountered, a floating-point disabled exception is taken.
The MDIS pin name has been changed to the JS0 pin and is included for boundary scan
purposes only.
1.1.2.1 ADDRESS TRANSLATION DIFFERENCES.
Although the MC68EC060 has no
paged MMU, the four transparent translation registers (ITT0, ITT1, DTT0, and DTT1) and
the default transparent translation (defined by certain bits in the translation control register
(TCR)) operate normally and can still be used to assign cache modes and supervisor and
write protection for given address ranges. All addresses can be mapped by the four trans-
parent translation registers (TTRs) and the default transparent translation.
1.1.2.2 INSTRUCTION DIFFERENCES.
The PFLUSH and PLPA instructions, the supervi-
sor root pointer (SRP) and user root pointer (URP) registers, and the E- and P-bits of the
TCR are not supported by the MC68EC060 and must not be used. Use of these instructions
and registers in the MC68EC060 exhibits poor programming practice since no useful results
can be achieved. Any functional anomalies that may result from their use will require system
software modification (to remove offending instructions) to achieve proper operation.
The PLPA instruction operates normally except that when an address misses in the four
TTRs, instead of performing a table search operation, the access cache mode and write pro-
tection properties are defined by the default transparent translation bits in the TCR. The
address register contents are never changed since all addresses are always transparently
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