IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
The BYPASS instruction becomes active on the falling edge of TCK in the update-IR state
when the data held in the instruction shift register is equivalent to $F.
9.1.3 JTAG Test Data Registers
The following paragraphs describe the JTAG test data registers. Idcode Register.
An IEEE-1149.1-compliant JTAG identification register has been
included on the MC68060. The MC68060 JTAG instruction encoded as $5 provides for read-
ing the JTAG idcode register. The format of this register is defined in Figure 9-2.
VERSION NO.—Version Number
Indicates the JTAG revision of the MC68060.
Bits 27–22
Indicate the high performance design center.
Bits 21–12
Indicate the device is a Motorola MC68060.
Bits 11–1
Indicate the reduced JEDEC ID for Motorola. (JEDEC refers to the Joint Electron Device
Engineering Council. Refer to JEDEC publication 106-A and chapter 11 of the IEEE
1149.1-1993 document for further information on this field.)
Bit 0
Differentiates this register as JTAG idcode (as opposed to the bypass register) according
to IEEE 1149.1. Boundary Scan Register.
An IEEE-1149.1-compliant boundary scan register has
been included on the MC68060. This 214-bit boundary scan register can be connected
between TDI and TDO when the EXTEST, LPSAMPLE, or SAMPLE/PRELOAD instructions
are selected. This register is used for capturing signal pin data on the input pins, forcing fixed
values on the output signal pins, and selecting the direction and drive characteristics (a logic
value or high impedance) of the bidirectional and three-state signal pins. Figure 9-3 through
Figure 9-7 depict the various cell types.
The key to using the boundary scan register is knowing the boundary scan bit order and the
pins that are associated with them. Below in Table 9-3 is the bit order starting from the TDI
input and going toward the TDO output.
31 28 27 22 21 12 11 1 0
VERSION NO. 0000010000110000000000011101
Figure 9-2. JTAG Idcode Register Format
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