IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
M68060 USER’S MANUAL
The LPSAMPLE instruction provides identical functionality to the
SAMPLE/PRELOAD instruction described in 18.104.22.168 SAMPLE/PRELOAD with one excep-
tion: instead of sampling the system data and control signals present at the MC68060 input
pins, the LPSAMPLE instruction forces the LPSTOP isolation transistors into isolation state
so that it can be verified that they are present and interrupting the path from the signal pin
to the internal logic.The LPSAMPLE instruction becomes active on the falling edge of TCK
in the update-IR state when the data held in the instruction shift register is equivalent to a $1.
22.214.171.124 Private Instructions.
The set of private instructions labeled MFG-TEST1 through
MFG-TEST9 are reserved by Motorola for internal manufacturing use. These instructions
can change (remap) the pin I/O and pin functions as defined for system operation (some
input pins may become output pins and some output pins may become input pins). Use of
these instructions without proper understanding can result in potentially destructive opera-
tion of the MC68060. These instructions become active on the falling edge of TCK in the
update-IR state when the data held in the instructions shift register is equivalent to values
$2, $3, $8, $9, $A, $B, $C, $D, and $E.
The SAMPLE/PRELOAD instruction provides two separate
functions. First, it provides a means to obtain a sample of the system data and control sig-
nals present at the MC68060 input pins and just prior to the boundary scan cell at the output
pins. This sampling occurs on the rising edge of TCK in the capture-DR state when an
instruction encoding of $4 is resident in the instruction register. The user can observe this
sampled data by shifting it through the boundary scan register to the output TDO by using
the shift-DR state. Both the data capture and the shift operation are transparent to system
operation. The user is responsible for providing some form of external synchronization to
achieve meaningful results since there is no internal synchronization between TCK and the
system clock, CLK.
The second function of the SAMPLE/PRELOAD instruction is to initialize the boundary scan
register update cells before selecting EXTEST or CLAMP. This is accomplished by ignoring
the data being shifted out of the TDO pin while shifting in initialization data. The update-DR
state in conjunction with the falling edge of TCK can then be used to transfer this data to the
update cells. This data will be applied to the external output pins when one of the instructions
listed previously is applied.
The IDCODE instruction selects the 32-bit idcode register for connection
as a shift path between the TDI pin and the TDO pin. This instruction allows the user to inter-
rogate the MC68060 to determine its JTAG version number and other part identification
data. The idcode register has been implemented in accordance with IEEE 1149.1 so that
the least significant bit of the shift register stage is set to logic one on the rising edge of TCK
following entry into the capture-DR state. Therefore, the first bit to be shifted out after select-
ing the idcode register is always a logic one (this is to differentiate a part that supports an
idcode register from a part that supports only the bypass register). The remaining 31-bits are
also set to fixed values (see
126.96.36.199 Idcode Register
) on the rising edge of TCK following
entry into the capture-DR state.
The IDCODE instruction is the default value placed in the instruction register when a JTAG
reset is accomplished by, either asserting TRST, or holding TMS high while clocking TCK