IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
M68060 USER’S MANUAL
*LPSAMPLE is not supported on version 0000. See Figure 9-2 in
188.8.131.52 Idcode Register
The EXTEST, SAMPLE/PRELOAD, and BYPASS instructions are required by IEEE 1149.1.
IDCODE is an optional public instruction supported by the MC68060. CLAMP and HIGHZ
are optional public instructions that are supported by the MC68060 and are described the
1149.1-1993 standard. LPSAMPLE is a Motorola-defined public instruction.
All encodings other than these are private instructions for Motorola internal use only.
Improper or unauthorized use of these instructions could result in potential internal damage
to the device and can cause external signal contention since these tests operate internal
registers, data path, and memory array logic and can drive random signal values on both
the input and output pins.
The external test instruction (EXTEST) selects the 214-bit boundary scan
register. The EXTEST instruction forces all output pins and bidirectional pins configured as
outputs to the fixed values that are preloaded (with the PRELOAD instruction) and held in
the boundary scan update registers. The EXTEST instruction can also be used to configure
the direction of bidirectional pins and establish high-impedance states on some pins. The
EXTEST instruction becomes active on the falling edge of TCK in the update-IR state when
the data held in the instruction shift register is equivalent to $0.
It is recommended that the boundary scan register bit equivalent to the RSTI pin be pre-
loaded with the assert value for system reset prior to application of the EXTEST instruction.
This will ensure that EXTEST asserts the internal reset for the MC68060 system logic to
force a predictable benign internal state while forcing all system output pins to fixed values.
However, if it is desired to hold the processor in the LPSTOP state when applying the
EXTEST instruction, do not preload the boundary scan register bit equivalent to the RSTI
pin with an assert value because this action forces the processor out of the LPSTOP state.
Table 9-2. JTAG Instructions
Instruction Acro Class IR3–IR0 Instruction Summary
EXTEST EXT Required 0000 Select boundary scan register to apply fixed values to outputs
LPSAMPLE LPS Public 0001 Selects the boundary scan register for data operations while
input pins are isolated *
MFG-TEST9 — Private 0010 For Motorola Internal Manufacturing Test use only
MFG-TEST1 — Private 0011 For Motorola Internal Manufacturing Test use only
SAMPLE SMP Required 0100 Selects boundary scan register for shift, sample and preload
IDCODE IDC Optional 0101 Defaults to select the ID code register
CLAMP CMP Optional 0110 Selects bypass while fixing output values
HIGHZ HIZ Optional 0111 Selects bypass while three-stating all chip outputs
MFG-TEST2 — Private 1000 For Motorola Internal Manufacturing Test use only
MFG-TEST3 — Private 1001 For Motorola Internal Manufacturing Test use only
MFG-TEST4 — Private 1010 For Motorola Internal Manufacturing Test use only
MFG-TEST5 — Private 1011 For Motorola Internal Manufacturing Test use only
MFG-TEST6 — Private 1100 For Motorola Internal Manufacturing Test use only
MFG-TEST7 — Private 1101 For Motorola Internal Manufacturing Test use only
MFG-TEST8 — Private 1110 For Motorola Internal Manufacturing Test use only
BYPASS BYP Required 1111 Selects the bypass register for data operations