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IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
MOTOROLA
M68060 USER’S MANUAL
9-3
9.1.2 JTAG Instruction Shift Register
The MC68060 IEEE 1149.1 implementation uses a 4-bit instruction shift register without par-
ity. The shift register transfers its value to a parallel hold register and applies one of sixteen
possible instructions, seven of which are defined as public customer-usable instructions, on
the falling edge of TCK when the TAP state machine is in the update-IR state (the other nine
instructions are private instructions to support manufacturing test and can cause destructive
behavior if used without proper understanding). The instructions may be loaded into the shift
portion of the register by placing the serial data on the TDI signal prior to each rising edge
of TCK. The most significant bit of the instruction shift register is the bit closest to the TDI
signal and the least significant bit is the bit closest to the TDO pin.
The public customer-usable instructions that are supported are listed with their encodings in
Table 9-2.
Figure 9-1. JTAG Test Logic Block Diagram
213 0
214-BIT BOUNDARY SCAN REGISTER
1-BIT BYPASS
0
32-BIT IDCODE REGISTER
31 0
4-BIT INSTRUCTION SHIFT REGISTER
INSTRUCTION APPLY & DECODE REGISTER
03
TDI
M
U
X
TDO
TAP CONTROLLER
TRST
TCK
TMS
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