Exception Processing
instruction is restarted, another table search is performed, and the instruction is executed
successfully. If the access is not allowed, it is up to the system software designer to deter-
mine appropriate action.
For the physical bus error cases, as long as it is not one of the non-recoverable write cases,
the exception handler must fix the page descriptor to point to a different physical memory,
so that when the restart of the instruction occurs, that bus error does not recur.
It is important to note that the MC68060 performs table searches in hardware, and does not
use the fetch table and page descriptors from the cache. The descriptor tables must be
placed in non-cachable memory so that when the exception handler touches these descrip-
tors, that the physical image in memory is updated properly.
The sixth step is to handle the default TTR cases. The default TTR is indicated if none of
these bits are set: TTR, PTA, PTB, IL and PF. At this point, only the following cases are pos-
WP = 1 (write protection violation detected by default TTR)
RE = 1 (bus error on read)
WE = 1 (bus error on write)
These cases may be handled similarly to step three. If the exception handler has gotten to
this point, but none of the WP, RE and WE bits are set, and if the BPE bit is set and has
been handled by the first step, then execute an RTE.
8.4.6 Bus Errors and Pending Memory Writes
The MC68060 processor contains two different write buffers for pending memory write oper-
ations: the store buffer and the push buffer. The store buffer is used to optimize performance
by deferring bus write operations in write through and imprecise cache modes, and the push
buffer holds displaced copyback mode cache lines and line write data for the MOVE16
The push buffer holds a displaced cache line destined for memory until the cache-miss bus
read access that caused the push completes. Imprecise cache modes (cachable write-
through and copyback, and cache inhibited, imprecise) use the write buffers of the MC68060
to optimize system performance. Cache inhibited precise mode provides a precise excep-
tion model for MC68060 operation, not utilizing the write buffers (store or push).
When the MC68060 detects an exception condition, all instruction execution is aborted and
the exception processing state is entered. Upon entering this state, the pipeline stalls until
both the store and push buffers are empty before beginning exception processing. If a TEA
signal termination occurs during a memory write cycle while emptying the store buffer, ‘a bus
error TEA on store buffer’ is recorded and the buffer sequences through all the remaining,
pending writes. However, if a TEA signal termination occurs during a memory write cycle
while emptying the push buffer, ‘a bus error TEA on push buffer’ is recorded and the memory
write operation is aborted immediately.
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