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Exception Processing
8-26 M68060 USER’S MANUAL MOTOROLA
The fourth step is to handle the paged memory management invalid descriptor cases. This
step is unnecessary if using an MC68EC060 or if the paged MMU is disabled. An invalid de-
scriptor is indicated by TTR = 0, and any one of the following bits are set: PTA, PTB, IL, PF,
and TWE. These bits indicate the cause of the access error and are mutually exclusive:
TWE = 1 (bus error detected during MMU table search reads or writes)
PTA = 1 (invalid root level descriptor)
PTB = 1 (invalid pointer-level descriptor)
IL = 1 (a second indirect level descriptor is encountered)
PF = 1 (invalid page descriptor)
Of the above cases, the TWE bit case must be handled with special care. Since no informa-
tion is given as to when the bus error is encountered, it is possible to encounter the bus error
again in the process of locating the fault.
The paged memory management architecture allows for only one level of indirection. A page
descriptor of type indirect must point to a page descriptor of type resident. If that second
page descriptor is of type invalid, an exception is taken such that PF = 1. If that second page
descriptor is of type indirect, a second level of indirection is attempted, and an exception is
taken such that IL = 1. If IL = 1, the handler must supply a page descriptor of type resident.
The PTA, PTB, PF cases require that the exception handler allocate physical memory for
the appropriate page and update the appropriate descriptor. When the instruction is
restarted, the table search either encounters the next table search fault or executes suc-
cessfully.
It is important to note that the MC68060 performs table searches in hardware and does not
use the fetch table and page descriptors from the cache. The descriptor tables must be
placed in noncachable memory so that when the exception handler touches these descrip-
tors, that the physical image in memory is updated properly.
Also note that since table searches that result in invalid descriptors (TWE, PTA, PTB, IL, PF)
do not update the ATC, the ATC need not be flushed by the exception handler.
The fifth step is to handle the paged memory management protection violation and bus error
cases. This step is unnecessary if using an MC68EC060 or if the paged MMU is disabled.
At this point, the table search has resulted in a valid page descriptor, and that the ATC has
been updated. As long as fourth step above is handled, following causes are possible and
are mutually exclusive:
SP = 1 (supervisor protection violation detected by paged MMU)
WP = 1 (write protection violation detected by paged MMU)
RE = 1 (bus error on read)
WE = 1 (bus error on write)
For the protection violation cases (SP and WP), if the access is to be allowed, the page
descriptor must be updated, and the corresponding ATC entry must be flushed. When the
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