Exception Processing
8.4.5 Recovering from an Access Error
The access error exception handler can identify the cause of the fault by examining the
FSLW. Unlike earlier processors, the MC68060 provides all the information needed to iden-
tify the fault by examining the FSLW. Note that this section does not discuss the use of the
SEE (software emulation error) bit nor does it provide the procedure needed to support the
M68060SP misaligned CAS and CAS2 emulation code. Refer to Appendix C MC68060
Software Package for details of how access error recovery is affected by the M68060SP.
The first step to recovering from an access error is for the exception handler to determine
whether or not a branch prediction error has occurred. See 8.4.7 Branch Prediction Error
for details on how a branch prediction error occurs. If the BPE bit in the FSLW is set, flush
the branch cache and continue with normal access error handling. If no other faults are indi-
cated, then execute an RTE and continue normal operations.
The second step for the handler is to determine whether or not the access error is recover-
able. In general, bus errors (TEA Asserted) on write cycles must be avoided. Refer to 8.4.6
Bus Errors and Pending Memory Writes for further details of bus errors and pending
memory writes. In summary, check for any of the following nonrecoverable write cases:
PBE = 1 (push buffer bus error)
SBE = 1 (store buffer bus error)
RW = 11, IO = 0, MA=1 (bus error on misaligned read-modify-write)
RW = 01, for a MOVE <ea>, <ea> in which the destination operand writes over the
source operand.
For these nonrecoverable write cases, the write reference has been lost and it is up to the
system software designer to determine the next course of action. Probably the most prudent
course of action is to discontinue the user program and enter a known supervisor state.
The third step is to handle the transparent translation access error cases. This is indicated
by TTR=1. All of these cases are recoverable as long as step two from above has been tak-
en out. At this point, the access error may be caused by the following errors, which are mu-
tually exclusive.
SP = 1 (supervisor protection violation detected by one of the four TTRs)
WP = 1 (write protection violation detected by one of the four TTRs)
RE = 1 (bus error on read)
WE = 1 (bus error on write)
For the SP = 1 or WP = 1 cases, it is possible to modify the transparent translation descriptor
to allow the access to occur once the instruction is restarted.
For the RE = 1 or WE = 1 cases, unless the cause of the bus error is removed, when the
instruction is restarted, the access error handler is re-entered, possibly resulting in an infinite
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