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Exception Processing
8-22 M68060 USER’S MANUAL MOTOROLA
I/O devices or peripherals that use multiple pages (paged MMU) to define the cache mode
and that cannot tolerate duplicate reads must not allow code that causes misaligned reads
that cross page boundaries. In this case, either use the TTRs or the default TTR to define
the I/O or peripheral cache mode. I/O devices or peripherals must not be accessed using
instructions which perform both read and write cycles (e.g., a memory-to-memory move)
unless the devices accessed are capable of handling rerun cycles caused by a processor
with a restart recovery model.
8.4.4.2 Fault Address. The fault address field contains the logical address of the access
that incurred the access error. The SIZE, TT, TM, R- and W-bits of the FSLW qualify the fault
address. For MMU-related exceptions (e.g., missing page faults, write protect, supervisor
protect), the fault address is the logical address calculated by the integer unit. For mis-
aligned operand access faults, the fault address points to the initial logical address calcu-
lated by the integer unit regardless of which bus cycle actually faulted. For instruction
extension word faults, this field points to the logical address of the instruction opword and
not the extension word.
8.4.4.3 Fault Status Long Word (FSLW) . The FSLW information indicates whether an
access to the instruction stream or the data stream (or both) caused the fault and contains
status information for the faulted access. Figure 8-6 illustrates the FSLW format.
Bits 31–28, 26, and 1—Reserved by Motorola.
IO, MA—Instruction or Operand, Misaligned Access
IO,MA
0, 0 = Fault occurred on the first access of a misaligned transfer, or to the
only access of an aligned transfer.
0, 1 = Fault occurred on the second or later access of a misaligned
transfer.
1, 0 = Fault occurred on an instruction opword fetch.
1, 1 = Fault occurred on a fetch of an extension word.
LK—Locked Transfer
0 =Fault did not occur on a locked transfer.
1 =Fault occurred on a locked transfer initiated by the processor (e.g., TAS, CAS, table
searches. Also set on locked transfers within the boundaries defined by the
MOVEC of BUSCR (LOCK bit) instruction.
Figure 8-6. Fault Status Long-Word Format
15 14 12 11 10 9 8 7 6 5432 1 0
PBE
SBE
PTA PTB IL PF SPIO
13
31 28 27 26 25 24 23 22 21 20 19 18 16
RESERVED MA RESERVED LK RW SIZE TMTT
WP TWE RE WE TTR BPE SEERESERVED
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