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MOTOROLA
M68060 USER’S MANUAL
1-1
SECTION 1
INTRODUCTION
The superscalar MC68060 represents a new line of Motorola microprocessor products. The
first generation of the M68060 product line consists of the MC68060, MC68LC060, and
MC68EC060. All three microprocessors offer superscalar integer performance of over 100
MIPS at 66 MHz. The MC68060 comes fully equipped with both a floating-point unit (FPU)
and a memory management unit (MMU) for high-performance embedded control and desk-
top applications. For cost-sensitive embedded control and desktop applications where an
MMU is required, but the additional cost of a FPU is not justified, the MC68LC060 offers
high-performance at a low cost. Specifically designed for low-cost embedded control appli-
cations, the MC68EC060 eliminates both the FPU and MMU, permitting designers to lever-
age MC68060 performance while avoiding the cost of unnecessary features. Throughout
this product brief, all references to the MC68060 also refer to the MC68LC060 and the
MC68EC060, unless otherwise noted.
Leveraging many of the same performance enhancements used by RISC designs as well
as providing innovative architectural techniques, the MC68060 harnesses new levels of per-
formance for the M68000 family. Incorporating 2.5 million transistors on a single piece of sil-
icon, the MC68060 employs a deep pipeline, dual issue superscalar execution, a branch
cache, a high-performance floating-point unit (MC68060 only), eight Kbytes each of on-chip
instruction and data caches, and dual on-chip demand paging MMUs (MC68060 and
MC68LC060 only). The MC68060 allows simultaneous execution of two integer instructions
(or an integer and a float instruction) and one branch instruction during each clock.
The MC68060 features a full internal Harvard architecture. The instruction and data caches
are designed to support concurrent instruction fetch, operand read and operand write refer-
ences on every clock. Separate 8-Kbyte instruction and 8-Kbyte data caches can be frozen
to prevent allocation over time-critical code or data. The independent nature of the caches
allows instruction stream fetches, data-stream fetches, and external accesses to occur
simultaneously with instruction execution. The operand data cache is four-way banked to
permit simultaneous read and write access each clock.
A very high bandwidth internal memory system coupled with the compact nature of the
M68000 family code allows the MC68060 to achieve extremely high levels of performance,
even when operating from low-cost memory such as a 32-bit wide dynamic random access
memory system.
Instructions are fetched from the internal cache or external memory by a four-stage instruc-
tion fetch pipeline. The MC68060 variable-length instruction system is internally decoded
into a fixed-length representation and channeled into an instruction buffer. The instruction
buffer acts as a FIFO which provides a decoupling mechanism between the instruction fetch
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