M68060 USER’S MANUAL
interrupting device using an interrupt acknowledge bus cycle with the interrupt level number
output on the transfer modifier signals. For a device that cannot supply an interrupt vector,
the autovector signal (AVEC) must be asserted. In this case, the MC68060 uses an inter-
nally generated autovector, which is one of vector numbers 25–31, that corresponds to the
interrupt level number (see Table 8-1). If external logic indicates a bus error during the inter-
rupt acknowledge cycle, the interrupt is considered spurious, and the processor generates
the spurious interrupt vector number, 24.
Once the vector number is obtained, the processor creates a stack frame of type 0. In this
stack frame, the processor saves the exception vector offset, PC value, and the internal
copy of the SR on the supervisor stack. The saved value of the PC is the logical address of
the next instruction had the interrupt not occurred.
Unlike previous processors of the M68000 family, the MC68060 defers interrupt sampling
from the beginning of exception processing of any exception, up to and until the first instruc-
tion of the exception handler. This allows the first instruction of any exception handler to
raise the interrupt mask level and therefore execute the exception handler without interrupts
(except level 7 interrupts).
Most M68000 family peripherals use programmable interrupt vector numbers as part of the
interrupt acknowledge operation for the system. If this vector number is not initialized after
reset and the peripheral must acknowledge an interrupt request, the peripheral usually
returns the vector number for the uninitialized interrupt vector, 15.
8.2.10 Reset Exception
Asserting the reset in (RSTI) input signal causes a reset exception. The reset exception has
the highest priority of any exception; it provides for system initialization and recovery from
catastrophic failure. Reset also aborts any processing in progress when RSTI is recognized;
processing cannot be recovered. Figure 8-5 is a flowchart of the reset exception processing.
The reset exception places the processor the supervisor mode by setting the S-bit and dis-
ables tracing by clearing the T-bit in the SR. This exception also sets the processor’s inter-
rupt priority mask in the SR to the highest level, level 7. Next the VBR is initialized to zero
($00000000), and all bits in the cache control register (CACR) for the on-chip caches are
cleared. The reset exception also clears the translation control register (TCR). It clears the
enable bit in each of the four transparent translation registers (TTRs). It also clears the bus
control register (BUSCR), and the PCR. The reset also affects the FPU. A quiet not-a-num-
ber (NAN) is loaded into each of the seven floating-point registers, and the floating-point
control register (FPCR), floating-point status register (FPSR), and floating-point instruction
address register (FPIAR) are cleared. If the processor is granted the bus, and the processor
does not detect TS asserted (possibly by an alternate master), the processor then performs
two long-word read bus cycles. The first long word, at address 0, is loaded into the SP, and
the second long word, at address 4, is loaded into the PC. Reset exception processing con-
cludes with the transfer of control to the memory location defined by the PC.
After the initial instruction is fetched, program execution begins at the address in the PC.
The reset exception does not flush the ATCs or invalidate entries in the instruction or data
caches; it does not save the value of either the PC or the SR. If an access error or address