Loading...
Exception Processing
8-12
M68060 USER’S MANUAL
MOTOROLA
When the MC68060 executes one of the breakpoint instructions, it performs a breakpoint
acknowledge cycle (read cycle) with an acknowledge transfer type (TT=$3) and transfer
modifier value of $0. Refer to
Section 7 Bus Operation
for a description of the breakpoint
acknowledge cycle. After external hardware terminates the bus cycle with either TA or TEA,
the processor performs illegal instruction exception processing. Refer to
8.2.4 Illegal
Instruction and Unimplemented Instruction Exceptions
for details on illegal instruction
exception processing.
8.2.9 Interrupt Exception
When a peripheral device requires the services of the MC68060 or is ready to send informa-
tion that the processor requires, it can signal the processor to take an interrupt exception
using the IPLx signals. The three signals encode a value of 0–7 (IPL0 is the least significant
bit). High levels on all three signals correspond to no interrupt requested (level 0). Values
1–7 specify one of seven levels of interrupts, with level 7 having the highest priority. Table
8-2 lists the interrupt levels, the states of IPLx that define each level, and the SR interrupt
mask value that allows an interrupt at each level.
When an interrupt request has a priority higher than the value in the interrupt priority mask
of the SR (bits 10–8), the processor makes the request a pending interrupt. Priority level 7,
the nonmaskable interrupt, is a special case. Level 7 interrupts cannot be masked by the
interrupt priority mask, and they are transition sensitive. The processor recognizes an
interrupt request each time the external interrupt request level changes from some lower
level to level 7, regardless of the value in the mask. Figure 8-3 shows two examples of
interrupt recognitions, one for level 6 and one for level 7. When the MC68060 processes a
level 6 interrupt, the SR mask is automatically updated with a value of 6 before entering the
handler routine so that subsequent level 6 interrupts and lower level interrupts are masked.
Provided no instruction that lowers the mask value is executed, the external request can be
lowered to level 3 and then raised back to level 6 and a second level 6 interrupt is not
processed. However, if the MC68060 is handling a level 7 interrupt (SR mask set to level 7)
and the external request is lowered to level 3 and than raised back to level 7, a second level
7 interrupt is processed. The second level 7 interrupt is processed because the level 7
interrupt is transition sensitive. A level comparison also generates a level 7 interrupt if the
request level and mask level are at 7 and the priority mask is then set to a lower level (as
Table 8-2. Interrupt Levels and Mask Values
Requested
Interrupt Level
Control Line Status Interrupt Mask Level Required
for Recognition
IPL2 IPL1 IPL0
0Negated Negated Negated No Interrupt Requested
1 Negated Negated Asserted 0
2 Negated Asserted Negated 0–1
3 Negated Asserted Asserted 0–2
4 Asserted Negated Negated 0–3
5 Asserted Negated Asserted 0–4
6 Asserted Asserted Negated 0–5
7 Asserted Asserted Asserted 0–7
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com