Exception Processing
Note that if the processor is executing in trace mode when a group 2 or 3 exception is sig-
naled, a trace exception will not be generated. This means that for the second example, as
the TRAP exception handler completes its execution and performs its RTE, the next instruc-
tion of the program sequence will be executed before the next trace exception is performed
(the MC68060 will not trace immediately after the TRAP). If tracing is required immediately
following a group 2 or 3 exception, the SR contained in the exception stack frame should be
checked before returning to the next instruction. If the stacked SR indicates that the proces-
sor was executing in trace mode, the trace handler should be executed to account for the
instruction that initiated the exception. Refer to
8.2 Integer Unit Exceptions
for a list of
group 2 or 3 exceptions.
Trace exception processing starts at the end of normal processing for the traced instruction
and before the start of the next instruction. As illustrated in Figure 8-1, the processor makes
an internal copy of the SR and enters the supervisor mode. It also clears the T-bit of the SR,
disabling further tracing. The processor supplies vector number 9 for the trace exception and
saves the trace exception vector offset, PC value, and the internal copy of the SR on the
supervisor stack. A stack frame of type 2 is generated when this exception is taken. The
stacked value of the PC is the logical address of the next instruction to be executed. In addi-
tion, the address field of the stack contains the logical address of the instruction that caused
the trace exception. Instruction execution resumes after the initial instruction is fetched from
the address in the privilege violation exception vector.
When the STOP or LPSTOP instruction is traced, the processor never enters the stopped
condition. A STOP or LPSTOP instruction that begins execution with the T-bit set forces a
trace exception after it loads the SR. Upon return from the trace exception handler, execu-
tion continues with the instruction following the STOP or LPSTOP instruction, and the pro-
cessor never enters the stopped condition.
8.2.7 Format Error Exception
Just as the processor verifies that the bit pattern contained in the operation word represents
a valid instruction, it also performs certain checks of data values for control operations. The
RTE and FRESTORE instruction check the validity of the stack format code. The RTE
instruction checks if the format field indicates a type supported by the processor (formats 0,
2, 3 or 4). Likewise, for FPU state frames, the FRESTORE instruction checks if the upper 8
bits of the status field contained in the floating-point state frame is valid ($00, $60, or $E0).
If any of these checks determine that the format of the data is improper, the instruction gen-
erates a format error exception. This exception saves a stack frame of type 0, generates
exception vector number 14, and continues execution at the address in the format exception
vector. The stacked PC value is the logical address of the instruction that detected the for-
mat error.
8.2.8 Breakpoint Instruction Exception
To provide increased debug capabilities in conjunction with a hardware emulator, the
MC68060 provides a series of breakpoint instructions ($4848–$484F) which generate a
special external bus cycle when executed.
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