M68060 USER’S MANUAL
Exception processing for illegal and unimplemented instructions is similar to that for instruc-
tion traps. When the processor has identified an illegal or unimplemented instruction, it ini-
tiates exception processing instead of attempting to execute the instruction. The processor
copies the SR, enters the supervisor mode, and clears T-bit, disabling further tracing. The
processor generates the vector number according to the exception type. The illegal or unim-
plemented instruction vector offset, current PC, and copy of the SR are saved on the super-
visor stack. Instruction execution resumes at the address contained in the exception vector.
8.2.5 Privilege Violation Exception
To provide system security, certain instructions are privileged. An attempt to execute one of
the following privileged instructions while in the user mode causes a privilege violation
ANDI to SR FSAVE MOVEC PLPA
CINV MOVE from SR MOVES RESET
CPUSH MOVE to SR ORI to SR RTE
EORI to SR MOVE USP PFLUSH STOP
Exception processing for privilege violations is similar to that for illegal instructions. When
the processor identifies a privilege violation, it begins exception processing before executing
the instruction. As illustrated in Figure 8-1, the processor copies the SR, enters the supervi-
sor mode, and clears the T-bit. The processor generates vector number 8, saves the privi-
lege violation vector offset, the current PC value, and the internal copy of the SR on the
supervisor stack. The saved value of the PC is the logical address of the first word of the
instruction that caused the privilege violation. Instruction execution resumes after the initial
instruction is fetched from the address in the privilege violation exception vector.
8.2.6 Trace Exception
To aid in program development, the M68000 family includes an instruction-by-instruction
tracing capability. In the trace mode, an instruction generates a trace exception after the
instruction completes execution, allowing a debugging program to monitor execution of a
In general terms, a trace exception is an extension to the function of any traced instruction.
The execution of a traced instruction is not complete until trace exception processing is com-
plete. If an instruction does not complete due to an access error or address error exception,
trace exception processing is deferred until after execution of the suspended instruction is
resumed. If an interrupt is pending at the completion of an instruction, trace exception pro-
cessing occurs before interrupt exception processing starts. If an instruction forces an
exception as part of its normal execution, the forced exception processing occurs before the
trace exception is processed.
The T-bit in the supervisor portion of the SR controls tracing. The state of the T-bit when an
instruction begins execution determines whether the instruction generates a trace exception
after the instruction completes.