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Exception Processing
MOTOROLA
M68060 USER’S MANUAL
8-9
number 11 and shares this vector with the floating-point disabled and the unimplemented F-
line exceptions. A stack frame of type 2 is generated when this exception is reported. The
stacked PC points to the logical address of the next instruction after the floating-point
instruction. Refer to
Section 6 Floating-Point Unit
for details.
A floating-point disabled exception occurs when the processor attempts to execute an
instruction word pattern that begins with $F, the processor recognizes this bit pattern as an
MC68881 instruction, but the FPU is disabled via the PCR, or if the processor is an
MC68LC060 or an MC68EC060. This exception corresponds to vector number 11 and
shares this vector with the floating-point unimplemented and the F-line Unimplemented
exceptions. A type 4 stack frame is generated when this exception is reported. The stacked
PC points to the logical address of the next instruction. The PC of the faulted instruction field
(SP+12) points to the floating-point instruction that needs to be emulated.
The effective address field (SP+8) contains the effective address of the source or destina-
tion of the memory operand for the floating-point instruction. This field is valid only if the
floating-point instruction references a memory operand. If the operand is in a register (either
floating-point or data register), the effective address field contains $0. For the (An)+ and
–(An) addressing modes, the address register is not modified by the processor, and it is the
responsibility of the third party emulation software to modify the An value before returning
to the user program. For the –(An) addressing mode, the value of the effective address field
contains the address of the first memory operand except if the operand size is extended pre-
cision. For the extended precision case, the effective address field contains An–4 instead of
An–12. This is a key difference between the MC68LC/EC060 and the MC68LC/EC040 stack
frame, and third-party software emulators written for the MC68LC/EC040 must account for
this difference.
An unimplemented F-line exception occurs when an instruction word pattern begins (bits
15–12) with $F, the MC68060 does not recognize it as a valid F-line instruction (e.g.,
PTEST), and the processor does not recognize it as a floating-point MC68881 instruction.
This exception corresponds to vector number 11 and shares this vector with the floating-
point unimplemented instruction and the floating-point disabled exceptions. A stack frame
of type 0 is generated by this exception. The stacked PC points to the logical address of the
F-line word.
If the processor encounters any other instruction word bit patterns that are not implemented
by the MC68060, and is not covered by one of the other six unimplemented instruction
exceptions, the illegal instruction exception is taken. The illegal instruction exception corre-
sponds to vector number 4. An illegal instruction exception is also taken after a breakpoint
acknowledge bus cycle is terminated, either by the assertion of the transfer acknowledge
(TA) or the transfer error acknowledge (TEA) signal. An illegal instruction exception can also
be a MOVEC instruction with an undefined register specification field in the first extension
word. The M68000 instruction set defines the opcode $4AFC as an ILLEGAL instruction.
This exception is also taken when that opcode is executed. A stack frame of type 0 is gen-
erated when this exception is taken. The stacked PC points to the logical address of the ille-
gal instruction that caused the exception.
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