M68060 USER’S MANUAL
since an RTE or FRESTORE instruction can check for residency and trap before restoring
A special case exists for systems that allow arbitration of the processor bus during locked
transfer sequences. If the arbiter can signal a bus error of a locked translation table update
due to an improperly broken lock, any pages touched by exception stack operations must
have the U-bit set in the corresponding page descriptor to prevent the occurrence of the
locked access during translation table searches.
8.2.2 Address Error Exception
An address error exception occurs when the processor attempts to prefetch an instruction
from an odd address. An odd address is defined as an address in which the least significant
bit is set. Some of the ways an address error exception is taken is as follows: RTS, RTD,
RTR, or RTE in which the PC value in the stack is odd; a branch (conditional or uncondi-
tional), jump, or subroutine call in which the branch target address is odd; and an odd vector
table entry (e.g., an odd reset vector).
A stack frame of type 2 is generated when this exception is reported.The stacked PC con-
tains the address of the instruction that caused the address error. The address field in the
stack contains the branch target address with A0 cleared.
If an address error occurs during the exception processing for a bus error, address error, or
reset, a double bus fault occurs. The processor enters the halted state as indicated by the
PST4–PST0 encoding $1C. In this case, the processor does not attempt to alter the current
state of memory. Only an external reset can restart a processor halted by a double bus fault.
8.2.3 Instruction Trap Exception
Certain instructions are used to explicitly cause trap exceptions. The TRAP #n instruction
always forces an exception and is useful for implementing system calls in user programs.
The TRAPcc, TRAPV, and CHK instructions force exceptions if the user program detects an
error, which can be an arithmetic overflow or a subscript value that is out of bounds. The
DIVS and DIVU instructions force exceptions if a division operation is attempted with a divi-
sor of zero.
As illustrated in Figure 8-1, when a trap exception occurs, the processor internally copies
the SR, enters the supervisor mode, and clears the T-bit. The processor generates a vector
number according to the instruction being executed. Vector 5 is for DIVx, vector 6 is for CHK,
and vector 7 is for TRAPcc and TRAPV instructions. For the TRAP #n instruction, the vector
number is 32 plus n. The stack frame saves the trap vector offset, the PC, and the internal
copy of the SR on the supervisor stack.
A stack frame of type 0 is generated when a TRAP #n exception is taken. The saved value
of the PC is the logical address of the instruction following the instruction that caused the
trap. Instruction execution resumes at the address in the exception vector after the required
instruction is prefetched.