Exception Processing
When the MC68060 detects any exception, the pipelines are aborted and exception pro-
cessing is initiated. After performing the SR copy and forcing the processor into the super-
visor mode, the processor then performs a pipeline synchronization to all the push and store
buffers to empty before proceeding with the exception. If a buffer bus error is signaled at this
time, the pipeline discards the original fault and instead reports the access error caused by
the first buffer write bus error (subsequent write buffer bus errors are ignored). Once the
push and store buffers are empty, the exception processing continues.
Processor accesses for either data or instructions can result in internal access errors. Inter-
nal access errors must be corrected to complete execution of the current instruction. An
internal access error occurs when the data or instruction memory management unit (MMU)
detects that a successful address translation is not possible because the page is write pro-
tected, supervisor only, or nonresident. When the instruction or data MMU detects that a
successful address translation is not possible, the instruction that initiated the unsuccessful
address translation is marked with an MMU fault and is continued down the pipeline. This
fault detection is independent of whether or not a table search was required. Some MMU
faults such as the supervisor-protect and write-protect faults can occur on address transla-
tion cache (ATC) hits or table searches. All other MMU faults can only occur on ATC misses
on the subsequent table searches. If this instruction that is marked with an MMU fault
reaches the EX stage of the OEP, an access error exception is reported.
As illustrated in Figure 8-1, the processor begins exception processing for an access error
by making an internal copy of the current SR. The processor then enters the supervisor
mode and clears the T-bit. The processor generates exception vector number 2 for the
access error vector. It saves the vector offset, PC, and internal copy of the SR on the stack.
In addition, the faulting logical address and the fault status long word (FSLW) is saved on
the stack.
A stack frame format of type 4 is generated when access error exception is reported. The
stacked PC is the logical address of the instruction executing at the time the fault was
detected. Note that this instruction is the instruction that initiated the bus cycle for all access
error cases, except for bus errors on write buffer (push or store) bus cycles. The logical
address that caused the fault is saved in the address field on the stack frame. Note that if
the fault occurred on the second or later of a misaligned access, the logical address may
need to be adjusted to point to the logical address that caused the access error. A fault sta-
tus long word is also provided in the stack to further qualify the conditions that caused the
If a bus error occurs during the exception processing for an access error, address error, or
reset, a double bus fault occurs, and the processor enters the halted state as indicated by
the PST4–PST0 encoding $1C. In this case, the processor does not attempt to alter the cur-
rent state of memory. Only an external reset can restart a processor halted by a double bus
The supervisor stack has special requirements to ensure that exceptions can be stacked.
The stack must be resident with correct protection in the direction of growth to ensure that
exception stacking never has a bus error or internal access error. Memory pages allocated
to the stack that are higher in memory than the current stack pointer can be nonresident
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