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Bus Operation
MOTOROLA M68060 USER’S MANUAL 7-75
loaded into the internal counter and the counter decrements every rising BCLK edge. As
long as the counter has a non-zero count value, the MC68060 ignores the acknowledge ter-
mination signals. Once the counter reaches zero, the MC68060 asserts SAS for one BCLK
period and begins to sample the acknowledge termination signals and acts accordingly. This
process repeats for the rest of the line transfer cycle.
To aid in system debug for system designs that continuously assert TA, a status signal,
SAS, is provided to indicate which rising BCLK edge the MC68060 begins to sample
acknowledge termination signals. SAS is negated on the next rising BCLK edge if the bus
cycle ends or if the next ignore state count value is non-zero. Aside from being a status sig-
nal, SAS may be used in conjunction with some decode address bits to generate the CLA
signal or TA signal shown in Figure 7-24.
Figure 7-51 shows an example of how the MC68060 behaves when the acknowledge termi-
nation ignore state mode is enabled. In this example, the read primary ignore state count
value and the read secondary ignore state count value are initialized to a value of one during
reset. On the first long-word access, TA is asserted immediately, but data is not registered
until the rising edge of C4. On the next long-word access, the secondary count value takes
effect. In a similar manner, TA is ignored until the rising edge of C6. On the last long-word
access of the line, the secondary ignore state count expires before TA is asserted. There-
fore, more wait states are added until TA is asserted and recognized on the rising edge of
C12.
Figure 7-51. Acknowledge Termination Ignore State Example
BCLK
ADDRESS AND
ATTRIBUTES
D31–D0
TS
SAS
R/W
C1 C2 C3 C4 C6 C7C5 C8
TA
C10 C11C9 C12
READ PRIMARY IGNORE STATE COUNT = 1
READ SECONDARY IGNORE STATE COUNT = 1
IGNORED IGNORED IGNORED IGNORED
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