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Bus Operation
MOTOROLA M68060 USER’S MANUAL 7-73
For processor resets after the initial power-on reset, RSTI should be asserted for at least ten
BCLK periods. Figure 7-49 illustrates timings associated with a reset when the processor is
executing bus cycles. BB and TIP are negated before transitioning to a three-state level.
Resetting the processor causes any bus cycle in progress to terminate as if TEA had been
asserted. In addition, the processor initializes registers appropriately for a reset exception.
Section 8 Exception Processing describes reset exception processing. When a RESET
bus operation instruction is executed, the processor drives the reset out (RSTO) signal for
512 CLK cycles. In this case, the processor can be used to reset external devices in a sys-
tem, and the internal registers of the processor are unaffected. The external devices con-
nected to the RSTO signal are reset at the completion of the RESET instruction. An RSTI
signal that is asserted to the processor during execution of a RESET instruction immediately
resets the processor and causes the RSTO signal to negate. RSTO can be logically ANDed
with the external signal driving RSTI to derive a system reset signal that is asserted for both
an external processor reset and execution of a RESET instruction.
Figure 7-49. Normal Reset Timing
BCLK
BUS
SIGNALS
RSTI
TS
BR
D15-D0,
IPL2–IPL0
BG
BB
TIP
t 10
BCLK CYCLES
27
CLK CYCLES
>
BTT
NOTE: For the processor to reset begin bus cycles after reset, BG must be asserted, TS must be negated or pulled up. BTT must be asserted (or BTT transition
from asserted to negated) eventually to indicate an end to the alternate master's tenure.
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