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Bus Operation
MOTOROLA M68060 USER’S MANUAL 7-71
7.13 RESET OPERATION
An external device asserts the reset input signal (RSTI) to reset the processor. When power
is applied to the system, external circuitry should assert RSTI for a minimum of ten BCLK
cycles after VCC is within tolerance. Figure 7-48 is a functional timing diagram of the power-
on reset operation, illustrating the relationships among VCC, RSTI, mode selects, and bus
signals. CLK is required to be stable by the time VCC reaches the minimum operating spec-
ification. CLK should start oscillating as VCC is ramped up in order to clear out contention
internal to the part caused by the random manner in which internal flip-flops power-up. RSTI
is internally synchronized for two BCLKs before being used and must meet the specified
Figure 7-47. Snooped Bus Cycle
BCLK
ALTERNATE
MASTER PROCESSOR
TT1
C1 C2 C3 C4 C5 C6
END-TEN AM-IMP SNOOP AM-EXP AM-EXP AM-EXP
A31–A0
BUS
ARBITRATION
STATE
D31–D0
TRANSFER
ATTRIBUTES
TS
TA
BR
BG
BB
AM_BR*
AM_BG*
*
AM indicates the alternate bus master.
BTT
SNOOP
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