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Bus Operation
MOTOROLA M68060 USER’S MANUAL 7-67
Figure 7-44 illustrates a functional timing diagram for an arbitration of a relinquish and retry
operation (MC68040 acknowledge termination mode). In Figure 7-44, the processor read
access that begins in C1 is terminated at the end of C2 with a retry request and BG negated,
forcing the processor to relinquish the bus and allow the alternate master to access the bus.
Note that the processor re-asserts BR during C3 since the original access is pending again.
After alternate bus master ownership, the bus is granted to the processor to allow it to retry
the access beginning in C7.
Figure 7-45 is a functional timing diagram for implicit ownership of the bus.
Figure 7-46 illustrates the effect of BGR on bus arbitration activity during locked sequences.
When BGR is asserted while BG is negated, locked sequences can be broken. Otherwise,
the entire locked sequence of bus cycles are completed by the processor before relinquish-
ing the bus.
Figure 7-43. Processor Bus Request Timing
A31–A0
BCLK
BUS
ARBITRATION
STATE
D31–D0
TRANSFER
ATTRIBUTES
TS
TA
ALTERNATE
MASTER PROCESSOR
BR
BG
BB
AM_BR*
AM_BG*
ALTERNATE
MASTER
C1 C2 C3 C4 C5 C8 C9C6 C7
*
AM indicates the alternate bus master.
BTT
C10
AM-EX AM-EX AM-EX EX-OWN EX-OWN END-TEN AM-IMPEX-OWN EX-OWN AM-EX
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