Bus Operation
is no longer needed. In an attempt to save time, the MC68060 negates BR. If BG takes too
long to assert, the MC68060 enters a disregard request condition.
The BR signal can be reasserted immediately for a different pending bus request, or it can
stay negated indefinitely. If an external bus arbiter is designed to wait for the MC68060 to
perform an active bus cycle before proceeding, then the system experiences an extended
period of time in which bus arbitration is dead-locked. It must be understood that BR is a
status signal which may or may not have any relationship to BB, BTT, or BG.
When using the MC68060-arbitration protocol it is possible to determine bus tenure bound-
aries by observing TS and BTT. An active bus tenure begins when a bus master asserts its
TS for the first time. Once the bus tenure has started, the active bus master must end its
tenure by asserting BTT (or a low-to-high transition of BB). If a bus master is granted the
bus, but does not start an active bus tenure by asserting TS, no BTT assertion (or a low-to-
high transition of BB) is needed since no bus tenure was started. When reset is applied to
the entire system, TS to all bus masters must be negated via a pullup resistor. In addition,
the bus arbiter must grant the bus to a single bus master. Once the first bus master recog-
nizes that TS is negated and that it has been granted the bus, it asserts its TS to establish
its bus tenure and to inform other bus masters that its bus tenure has begun (this assumes
that the TS signals of all bus masters in the system are tied together). All other bus masters
will therefore detect an asserted TS (TS is asserted by the first bus master) immediately
after reset. These bus masters must then wait for BTT to assert (or a low-to-high transition
of BB) before beginning their bus tenure when granted the bus.
Figure 7-43 illustrates an example of the processor requesting the bus from the external bus
arbiter. During C1, the MC68060 asserts BR to request the bus from the arbiter, which
negates the alternate bus master’s BG signal and grants the bus to the processor by assert-
ing BG during C2. During C2, the alternate bus master completes its current access and
relinquishes the bus in C3 by three-stating all bus signals and negating BB and/or asserting
BTT. Typically, the BB and BTT signals require a pullup resistor to maintain a logic-one level
between bus master tenures. The alternate bus master should negate these signals before
three-stating to minimize rise time of the signals and ensure that the processor recognizes
the correct level on the next BCLK rising edge. At the end of C3, the processor has already
received bus grant and the alternate master has relinquished the bus. Hence, the processor
assumes ownership of the bus and immediately begins a bus cycle during C4. During C6,
the processor begins the second bus cycle for the misaligned operand and negates BR
since no other accesses are pending. During C7, the external bus arbiter grants the bus
back to the alternate bus master that is waiting for the processor to relinquish the bus. The
processor negates BB, asserts BTT, and three-states bus signals during C8. Finally, the
alternate bus master has the bus grant. The processor has relinquished the bus at the end
of C8 and is able to resume bus activity during C9. Note that BTT is asserted only for one
BCLK period and is negated for one BCLK period during C10. BTT is then three-stated in
Further note that BB is only negated for one CLK (as opposed to BCLK) period before being
three-stated, and the MC68040-arbitration protocol should not be used for full bus speed
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