Bus Operation
The snoop state is similar to the AM-explicit own state in that the MC68060 does not have
ownership of the bus. The snoop state differs from the AM-explicit own state in that the
MC68060 is in the process of performing an internal snoop operation because the processor
has detected that TS and SNOOP are asserted and TT1 = 0. The snoop state always returns
to the AM-explicit own state. The implicit ownership state indicates that the MC68060 owns
the bus because BG is asserted to it. The processor, however, is not ready to begin a bus
cycle, and keeps BB negated and the bus three-stated until an internal bus request occurs.
The MC68060 explicitly owns the bus when the bus is granted to it (BG asserted) and it has
initiated at least one bus cycle. Until BG is negated, the processor retains explicit ownership
of the bus whether or not active bus cycles are being executed. When the processor is ready
to relinquish the bus, it goes through the end tenure state to indicate to all alternate masters
that it is relinquishing the bus. During the end tenure state, BTT is asserted for one BCLK
and is actively negated for the next BCLK prior to three-stating. While in this state, if RSTI
is asserted, the processor proceeds to the end tenure state to inform other bus masters it is
relinquishing the bus.
All alternate masters that reside in a system and use the MC68060-arbitration protocol must
provide the same functionality as the MC68060 for proper system operation.
7.11.3 External Arbiter Considerations
The bus arbitration state diagrams for the MC68040-arbitration protocol and MC68060-arbi-
tration protocol may be used to approximate the high level behavior of the processor. In
either case, it is assumed that all TS signals in a system are tied together, all BB signals in
a system are tied together and to a pullup resistor (MC68040-arbitration protocol), or all BTT
signals in a system are tied together and to a pullup resistor (MC68060-arbitration protocol).
Furthermore, unused BB or BTT pins must have separate pullup resistors.
If an alternate master loses bus ownership when it is in its implicit ownership state, the pro-
cessor checks TS. If TS is sampled asserted, the processor interprets this as the alternate
master transitioning to its explicit ownership state, and it does not take over bus ownership.
This operation is different from that of the MC68040, in that external arbiters are required to
check for this boundary condition. However, in order for the processor to properly detect this
boundary condition, it is imperative that the TS of all alternate bus masters be tied together
with the processor’s TS signal.
When using the MC68040-arbitration protocol, as with the TS signal, the BB of all alternate
bus masters must be tied together to the processor’s BB signal. Also, when an alternate
master becomes bus master, it must assert BB if it initiates a bus cycle with the TS asserted.
The external arbiter design needs to include the function of BR. For example, in certain
cases associated with conditional branches, the MC68060 can assert BR to request the bus
from an alternate bus master, then negate BR without using the bus, regardless of whether
or not the external arbiter eventually asserts BG. This situation happens when the MC68060
attempts to prefetch an instruction for a conditional branch. To achieve maximum perfor-
mance, the processor may prefetch the instructions of the forward path for a conditional
branch. If the branch prediction is incorrect and if the conditional branch results in a branch-
not-taken, the previously issued branch-taken prefetch is then terminated since the prefetch
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