Bus Operation
The MC68060 can be in any one of seven bus arbitration states during bus operation: reset,
AM-implicit own, AM-explicit own, snoop, implicit ownership, explicit ownership, and the end
tenure state.
The reset state is entered whenever RSTI is asserted in any bus arbitration state, except the
explicit ownership state. For that state, the end tenure state is entered prior to entering the
reset state.This is done to ensure other bus masters are capable of taking the bus away from
the processor when it is reset. When RSTI is negated, the processor proceeds to the implicit
ownership state or alternate master implicit ownership state, depending on BG. If an alter-
nate master asserts TS or has asserted TS in the past, the processor waits for BTT to assert
(or alternatively for BB to go from being asserted to being negated) before taking the bus,
even though BG may be asserted to the processor.
The AM-implicit own state denotes the MC68060 does not have ownership (BG negated) of
the bus and is not in the process of snooping an access, and the alternate has not begun its
tenure by asserting TS (alternate master TS or SNOOP negated). In the AM-implicit own
state, the MC68060 does not drive the bus. The processor enters the AM-explicit own state
when TS is asserted by the alternate master. Once in the AM-explicit own state, the proces-
sor waits for the alternate master to assert BTT before recognizing that a change of tenure
has occurred. If BG is negated when BTT is asserted, the processor assumes that another
master has taken implicit ownership of the bus. Otherwise, if BG is asserted when BTT is
asserted, the processor assumes implicit ownership of the bus.
If an alternate master loses bus ownership when it is in implicit ownership state, the proces-
sor checks TS. If TS is sampled asserted, the processor interprets this as the alternate mas-
ter transitioning to its explicit ownership state, and it does not take bus ownership. This
operation is different from that of the MC68040 in that external arbiters are required to check
for this boundary condition. However, in order for the processor to properly detect this
boundary condition, it is imperative that the TS of all alternate bus masters be tied together
with the processor’s TS signal.
Table 7-9. MC68060-Arbitration Protocol State Description
BTTO Bus Status Own State
Not Driven Not Driven No Reset
Not Driven Not Driven No Alternated Master Implicit Own
Not Driven Not Driven No Alternate Master Explicit Own
Not Driven Not Driven Yes Implicit Ownership
Not Driven Driven Yes Explicit Ownership
Asserted for One
BCLK, Negated for
One BCLK then
Stops Being
Driven at End
of State Yes End Tenure
Not Driven Not Driven No Alternate Master Own and Snooped
NOTE: BTTO represents the component of BTT as driven by the MC68060. BTT is normal-
ly three-stated but driven for one BCLK when asserted and one BCLK when negated.
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