Bus Operation
The snoop state is similar to the AM-explicit own state in that the MC68060 does not have
ownership of the bus. The snoop state differs from the AM-explicit own state in that the
MC68060 is in the process of performing an internal snoop operation because the processor
has detected that TS and SNOOP are asserted and TT1 = 0. The snoop state always returns
to the AM-explicit own state.
The implicit ownership state indicates that the MC68060 owns the bus because BG is
asserted to it. The processor, however, is not ready to begin a bus cycle, and it keeps BB
negated and the bus three-stated until an internal bus request occurs.
The MC68060 explicitly owns the bus when the bus is granted to it (BG asserted) and at
least one bus cycle has initiated. The processor asserts BB during this state to indicate the
processor has explicit ownership of the bus. Until BG is negated, the processor retains
explicit ownership of the bus whether or not active bus cycles are being executed. When the
processor is ready to relinquish the bus, it goes through the end tenure state to indicate to
all alternate masters that it is relinquishing the bus. During the end tenure state, BB goes
from being actively asserted to being actively negated for one CLK cycle and then three-
stated. While in this state, RSTI is asserted and the processor proceeds to the end tenure
state to inform other bus masters it is relinquishing the bus.
7.11.2 MC68060-Arbitration Protocol (BTT Protocol)
The MC68060-arbitration protocol is different from the MC68040-arbitration protocol in that
BTT is used instead of BB. BTT indicates that the MC68060 has completed a bus tenure
and the bus can now be used by another master. When using the MC68060-arbitration pro-
tocol, BB must be pulled high via a separate pullup resistor since the processor drives BB
during bus tenure times. This pullup resistor must be used solely for BB.
Arbitration within the MC68060 bus interface controller is based on current bus ownership
and the concept that a bus cycle is an atomic entity which cannot be split, though it may be
prematurely terminated. If the bus is currently owned by the processor, it can be owned by
another master only after the completion of the final bus cycle when the processor has
asserted BTT.
If the bus is not currently owned by the processor, it asserts its BR signal as soon as it needs
the bus. Bus mastership is assumed as soon as the assertion of BG is received from the bus
arbiter and the one BCLK period assertion of the bused BTT is detected (or alternately, the
transition and negation of BB is detected at a rising BCLK edge), indicating the previous
master has terminated its tenure and relinquished the bus. If the MC68060 still has a need
to use the bus when BG is received, it assumes bus mastership, asserts TS, and starts a
bus cycle. Note the MC68060 negates its BR signal if, due to internal state, it no longer
needs to use the bus at that moment in time. It negates its BR signal at the same time it
asserts the TS signal if the bus is only needed for one bus cycle.
BTT is connected to all masters in a system to give notice of the termination of bus tenure
by the MC68060 processor. BTT is asserted by the MC68060 after it has lost right of own-
ership to the bus by the negation of BG and is ready to end usage of the bus. After the final
termination acknowledgment of the final bus cycle when the MC68060 has lost bus owner-
ship, the processor asserts BTT for a one BCLK period, negates BTT for a one BCLK period,
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