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Bus Operation
MOTOROLA M68060 USER’S MANUAL 7-55
Table 7-6. MC68040-Arbitration Protocol Transition Conditions
Present
State Condition RSTI BG
TS
sampled
as an
input
TSI
SNOOP
BB
sampled
as an
input
(BBI)
Internal
Bus
Request
(IBR)
Transfer in
Progress?
End of
Cycle? Next State
Reset
A1 A — — — — Reset
A2 A A Implicit Own
A3 N N AM Implicit
Explicit
Own
B1 N N N End Tenure
B2 N N A N Explicit Own
B3 N N A A End Tenure
B4 N A Explicit Own
End
Tenure
C1 N N N N AM Implicit
C2 N A N Implicit Own
C3 N A A Explicit Own
C4 N N A — — — Violation
C5 N N A — — — Violation
AM
Implicit
D1 N A A — — — Snoop
D2 N A N AM Explicit
D3 N N N AM Implicit
D4 N A N N N Implicit Own
D5 N A N N A Explicit Own
D6 N A N A AM Explicit
AM
Explicit
E1 N A A — — — Snoop
E2 N A N AM Explicit
E3 N N A AM Explicit
E4 N A N N N Implicit Own
E5 N A N N A Explicit Own
E6 N N N N AM Implicit
Implicit
Own
F1 N N N AM Implicit
F2 N A N Implicit Own
F3 N A A Explicit Own
F4 N N A — — — Violation
Snoop G1 AM Explicit
Any A — — — — Reset
NOTES:
1) “N” means negated; “A” means asserted.
2) End of Cycle: Whatever terminates a bus transaction whether it is normal, bus error, or retried. Note that ong-word
bus cycles that result from a burst-inhibited line transfer are considered part of that original line transfer.
3) Conditions C4, C5, and F4 indicate that an alternate master has taken ownership without sampling B
B as negated.
4) IBR refers to an internal bus request. The output signal BR is a registered version of IBR.
5) BBI refers to BB when sampled as an input.
6) SNOOP denotes the condition in which SNOOP is sampled asserted and TT1 = 0.
7) In this state diagram, BGR is assumed always asserted, hence, bus cycles within a locked sequence are treated no
differently from nonlocked bus cycles, except that the processor takes an extra BCLK period in the end tenure state
to allow for LOCK and LOCKE to negate. If BGR is negated and a locked sequence is in progress, the processor
does not relinquish the bus if BG is negated until the end of the last bus cycle in the locked sequence.
8) The processor does not require a valid acknowledge termination for snooped accesses. The only restriction is that
a snoop cycle be performed at no more than a maximum rate of once every two BCLK cycles. This state diagram
properly emulates this behavior.
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