Bus Operation
relinquish the bus. But, if the alternate master is another MC68060, it may not be advisable
to allow locked sequences to be broken. Figure 7-46 illustrates BGR functionality on locked
When the bus has been granted to the processor in response to the assertion of BR, one of
two situations can occur. In the first situation, the processor monitors BB and TS to deter-
mine when the bus cycle of the alternate bus master is complete and to guarantee that
another master has not already started another bus tenure. After the alternate bus master
negates and three-states BB, the processor asserts BB to indicate explicit bus ownership
and begins the bus cycle by asserting TS. The processor continues to assert BB until the
external arbiter negates BG, after which BB is driven negated at the completion of the bus
cycle, then forced to a high-impedance state. As long as BG is asserted, BB remains
asserted to indicate the bus is owned, and the processor continuously drives the address
bus, attributes, and control signals. The processor negates BR when there are no pending
internal requests to allow the external arbiter to grant the bus to an alternate bus master if
In the second situation, the processor samples BB until the alternate master negates BB.
Then the processor takes implicit ownership of the bus. Implicit ownership of the bus occurs
when the processor is granted the bus, but there are no pending bus cycles. The MC68060
does not drive the bus and BB if the bus is implicitly owned. This is different from the
MC68040 which drives the address, attributes, and control signals during implicit ownership
of the bus. If an internal access request is generated, the processor assumes explicit own-
ership of the bus and immediately begins an access, simultaneously asserting BB, BR, TIP,
and TS. If the external arbiter keeps BG asserted to the processor, the processor keeps BB
asserted and either executes active bus cycles or drives the address and attributes with
undefined values in-between active bus cycles.
BR can be used by the external arbiter as an indication that the processor needs the bus.
However, there is no guarantee that when the bus is granted to the processor, that a bus
cycle will be performed. At best, BR must be used as status output that the processor needs
the bus, but not as an indication that the processor is in a certain bus arbitration state. Figure
7-41 provides a high-level arbitration diagram that can be used by external arbiters to predict
how the MC68060 operates as a function of external signals, and internal signals. For
instance, note that the relationship between the internal BR and the external BR is best
described as a synchronous delay off BCLK.
Figure 7-41 is a bus arbitration state diagram for the MC68040 bus arbitration protocol.
Table 7-6 lists conditions that cause a change to and from the various states. Table 7-7 lists
a summary of the bus conditions and states.
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