Bus Operation
provided for compatibility with existing MC68040-based ASICs and logic. This arbitration
protocol uses the BR, BG, and BB signals. Bus tenure terminated (BTT) must be ignored by
the external arbiter and pulled high using a separate pullup resistor on the MC68060 pin
when using this arbitration protocol.
In addition to the MC68040-arbitration protocol, a high speed MC68060-arbitration protocol
is introduced to provide arbitration activity at higher frequencies. This arbitration protocol
uses the BR, BG, BTT, and BGR signals. BB must be ignored by the external arbiter and
pulled high using a separate pullup resistor on the MC68060 when using this arbitration pro-
In either arbitration protocol, the bus arbitration unit in the MC68060 operates synchronously
and transitions between states in which CLK is enabled via CLKEN asserted (on the rising
edge of BCLK). Either arbitration protocol allows arbitration to overlap with bus activity, but
the MC68040-arbitration protocol should not be used at full bus speed. With either arbitra-
tion protocol, each master which can initiate bus cycles must have their TS signals con-
nected together so that the MC68060 can maintain proper internal state. Note also, when
using the MC68040-arbitration protocol, any alternate master which takes over bus owner-
ship and initiates bus cycles with the assertion of TS must also assert BB for the time of its
bus tenure.
7.11.1 MC68040-Arbitration Protocol (BB Protocol)
When using the MC68040-arbitration protocol, BTT must be pulled high through a resistor.
Since BTT is also an output, a separate pullup resistor must be used exclusively for BTT.
The MC68060 requests the bus from the external bus arbiter by asserting BR whenever an
internal bus request is pending. The processor continues to assert BR for as long as it
requires the bus. The processor negates BR at any time without regard to the status of BG
and BB. If the bus is granted to the processor when an internal bus request is generated,
BR is asserted simultaneously with transfer start (TS), allowing the access to begin imme-
diately. The processor always drives BR, and BR cannot be wire-ORed with other devices.
The external arbiter asserts BG to indicate to the processor that it has been granted the bus.
If BG is negated while a bus cycle is in progress, the processor relinquishes the bus at the
completion of the bus cycle, except on locked sequences in which BGR is negated. To guar-
antee that the bus is relinquished, BG must be negated prior to the rising edge of the BCLK
in which the last TA, TEA, or TRA is asserted. Note that the bus controller considers the four
long-word bus transfers of a burst-inhibited line transfer to be a single bus cycle and does
not relinquish the bus until completion of the fourth transfer.
Unlike the MC68040 in which the read and write portions of a locked sequence is divisible,
the MC68060 provides a choice via the BGR input. If BGR is asserted when BG is negated
in the middle of a locked sequence, the MC68060 operates like the MC68040 and relin-
quishes the bus after the current bus cycle is completed. Otherwise, if BGR is negated when
BG is negated, the MC68060 ignores the negated BG, retains bus ownership, and com-
pletes all bus cycles of the locked sequence before giving up the bus. Systems may use the
BGR input to assign severity of the BG negation. For instance, if bus arbitration is used to
allow for DRAM refresh, it is okay to ignore locked sequences and force the MC68060 to
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