Bus Operation
A second access or address error that occurs during execution of an exception handler or
later, does not cause a double bus fault. A bus cycle that is retried does not constitute a bus
error or contribute to a double bus fault. The processor continues to retry the same bus cycle
as long as external hardware requests it.
The MC68060 integer unit generates access requests to the instruction and data memory
units to support integer and floating-point operations. Both the <ea> fetch and write-back
stages of the integer unit pipeline perform accesses to the data memory unit. All read and
write accesses are performed in strict program order. Compared with the MC68040, the
MC68060 is always “serialized’. This feature makes it possible for automatic bus synchroni-
zation without requiring NOPs between instructions to guarantee serialization of reads and
writes to I/O devices.
The instruction restart model used for exception processing in the MC68060 may require
special care when used with certain peripherals. After the operand fetch for an instruction,
an exception that causes the instruction to be aborted can occur, resulting in another access
for the operand after the instruction restarts. For example, an exception could occur after a
read access of an I/O device’s status register. The exception causes the instruction to be
aborted and the register to be read again. If the first read accesses clears the status bits,
the status information is lost, and the instruction obtains incorrect data.
The bus design of the MC68060 provides for one bus master at a time, either the MC68060
or an external device. More than one device having the capability to control the bus can be
attached to the bus. An external arbiter prioritizes requests and determines which device is
granted access to the bus. Bus arbitration is the protocol by which the processor or an exter-
nal device becomes the bus master. When the MC68060 is the bus master, it uses the bus
to read instructions and transfer data not contained in its internal caches to and from mem-
ory. When an alternate bus master owns the bus, the MC68060 can be made to monitor the
alternate bus master’s transfer and maintain cache coherency. This capability is discussed
in more detail in 7.12 Bus Snooping Operation.
Like the MC68040, the MC68060 implements an arbitration method in which an external
arbiter controls bus arbitration and the processor acts as a slave device requesting owner-
ship of the bus from the arbiter. Since the user defines the functionality of the external arbi-
ter, it can be configured to support any desired priority scheme. For systems in which the
processor is the only possible bus master, the bus can be continuously granted to the pro-
cessor, and no arbiter is needed. Systems that include several devices that can become bus
masters require an arbiter to assign priorities to these devices so, when two or more devices
simultaneously attempt to become the bus master, the one having the highest priority
becomes the bus master first. The MC68060 bus interface controller generates bus
requests to the external arbiter in response to internal requests from the instruction and data
memory units.
The MC68060 supports two bus arbitration protocols. These arbitration protocols are mutu-
ally exclusive and must not be mixed in a system. An MC68040-style arbitration protocol is
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