Bus Operation
When the processor recognizes a bus error condition for an access, the access is termi-
nated immediately. A line access that has TEA asserted for one of the four long-word trans-
fers aborts without completing the remaining transfers, regardless of whether the line
transfer uses a burst or burst-inhibited access.
When a bus cycle is terminated with a bus error, the MC68060 can enter access error
exception processing immediately following the bus cycle, or it can defer processing the
exception. The instruction prefetch mechanism requests instruction words from the instruc-
tion memory unit before it is ready to execute them. If a bus error occurs on an instruction
fetch, the processor does not take the exception until it attempts to use the instruction.
Should an intervening instruction cause a branch or should a task switch occur, the access
error exception for the unused access does not occur. Similarly, if a bus error is detected on
the second, third, or fourth long-word transfer for a line read access, an access error excep-
tion is taken only if the execution unit is specifically requesting that long word. The line is not
placed in the cache, and the processor repeats the line access when another access refer-
ences the line. If a misaligned operand spans two long words in a line, a bus error on either
the first or second transfer for the line causes exception processing to begin immediately. A
bus error termination for any write access or read access that reference data specifically
requested by the execution unit causes the processor to begin exception processing imme-
diately. Refer to Section 8 Exception Processing for details of access error exception pro-
When a bus error terminates an access, the contents of the corresponding cache can be
affected in different ways, depending on the type of access. For a cache line read to replace
a valid instruction or data cache line, the cache line is untouched if the replacement line read
terminates with a bus error. If a dirty data cache line is being replaced, the dirty line is placed
in the push buffer and is eventually written out to memory. This is done whether or not a bus
error occurs during the replacement line read. If any cache push results in a bus error ter-
mination, the cache push data is lost.
Write accesses to memory pages specified as cachable writethrough by the data memory
unit update the corresponding cache line before accessing memory. If a bus error occurs
during a memory access, the cache line remains valid with the new data. For noncachable
precise memory pages, the cache line is not updated if the write cycle terminates with a bus
error. Figure 7-37 illustrates a functional timing diagram of a bus error on a word write
access causing an access error exception. Figure 7-38 illustrates a functional timing dia-
gram of a bus error on a line read access that does not cause an access error exception.
In general, write cycles that result in bus error termination must be avoided. The MC68060
has write and push buffers to decouple the processor from the system. Before the processor
writes into the write and push buffers, access errors that result from address translation
cache (ATC) faults should have been reported via an access error exception and eventually
fixed by the access error handler. Since the instruction that reports the bus error on the write
cycle usually is not the instruction that causes the write, it is not possible to recover that write
cycle via an instruction restart. Although the fault address indicates the logical address of
the write cycle that incurred the bus error, the write data information is not available in the
access error stack. As such, this access error case is nonrecoverable unless the system is
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