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Bus Operation
7-40 M68060 USER’S MANUAL MOTOROLA
To exit the LPSTOP mode, the processor CLK must be restarted for at least eight CLK and
two BCLK periods prior to asserting either the RSTI or generating an interrupt. It is impera-
tive before asserting RSTI or generating the interrupt no alternate master activity be done
until the processor begins exception processing for either the reset or interrupt. Additionally,
the following control signals must be pulled-up or negated during this time: BB, TRA, TA,
TEA, CLA, BGR, BG, SNOOP, AVEC, MDIS, CDIS, TCI, and TBI. The processor uses the
PSTx encoding of $18 to indicate exception processing.
Figure 7-31. Breakpoint Interrupt Acknowledge Bus Cycle Timing
C1 C2
BREAKPOINT
ACKNOWLEDGE
C1 C2
WRITE STACK
A31–A0
BCLK
SIZ1–SIZ0
UPA1–UPA0
D31–D0
TM2–TM0
TT1–TT0
TS
TIP
TA
R/W
BS0
CIOUT
SAS
BS3–BS1
BYTE
MISCELLANEOUS
ATTRIBUTES
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