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Bus Operation
7-38 M68060 USER’S MANUAL MOTOROLA
7.8.2.1 LPSTOP BROADCAST CYCLE. The execution of an LPSTOP instruction gener-
ates the LPSTOP broadcast cycle. This access is a write bus cycle and is indicated with
TT1, TT0 = $3, A31–A0 = $FFFFFFFE, and TM2–TM0 = $0. When an external device ter-
minates the cycle with either TA or TEA, the processor enters the low-power stop mode. A
Figure 7-29. Autovector Interrupt Acknowledge Bus Cycle Timing
C1 C2
INTERRUPT
ACKNOWLEDGE
AUTOVECTORED
AVEC
C1 C2
WRITE STACK
A31–A0
BCLK
SIZ1–SIZ0
UPA1–UPA0
D31–D0
TM2–TM0
TT1–TT0
TS
TIP
TA
R/W
BS3
CIOUT
SAS
BS2–BS0
BYTE
INTERRUPT LEVEL
MISCELLANEOUS
ATTRIBUTES
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