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Bus Operation
7-36 M68060 USER’S MANUAL MOTOROLA
and if TA and TEA are both asserted, the processor retries the cycle. If operating in native-
MC68060 acknowledge termination mode, a retry is indicated by the assertion of TRA.
Note that the acknowledge termination ignore state capability is applicable to the interrupt
acknowledge cycle. If enabled, TA, TEA, TRA, and other acknowledge termination signals
are ignored for a user-programmed number of BCLK cycles.
7.8.2 Breakpoint Acknowledge Cycle
The execution of a BKPT instruction generates the breakpoint acknowledge cycle. An
acknowledged access is a read bus cycle and is indicated with TT1, TT0 = $3, address A31–
A0 = $00000000, and TM2–TM0 = $0. When the external device terminates the cycle with
either TA or TEA, the processor takes an illegal instruction exception. A retry termination
simply retries the breakpoint acknowledge cycle. Figure 7-30 and Figure 7-31 illustrate a
flowchart and functional timing diagram for a breakpoint acknowledge bus cycle.
Figure 7-27. Interrupt Acknowledge Cycle Flowchart
1) IPEND RECOGNIZED. WAIT FOR INSTRUC-
TION BOUNDARY OR LOCK NEGATED
2) SET R/W TO READ
3) DRIVE ADDRESS ON A31–A0 TO $FFFFFFFF
4) DRIVE UPA1–UPA0 = 0
5) DRIVE TT1–TT0 = 3
6) DRIVE TM2–TM0 = INTERRUPT LEVEL
7) DRIVE TLN1–TLN0 = 0
8) ASSERT BS3
9) NEGATIVE CIOUT, LOCK, LOCKE, BS2–BS0
10) DRIVE SIZ1–SIZ0 TO BYTE
11) ASSERT TS FOR ONE BCLK
12) ASSERT TIP
13) ASSERT SAS IMMEDIATELY IF
ACKNOWLEDGE TERMINATION IGNORE
STATE CAPABILITY DISABLED. ELSE,
ASSERT SAS AFTER READ PRIMARY
IGNORE STATE COUNTER HAS EXPIRED
1) ASSERT IPL2–IPL0 SUCH THAT INTERRUPT
LEVEL GREATER THAN MASK LEVEL IN SR
1) DECODE ADDRESS AND ATTRIBUTES
2) EITHER PLACE VECTOR ON D7–D0 OR
ASSERT AVEC
3) ASSERT TA, TEA, OR TRA FOR ONE BCLK
1) IF NORMAL TERMINATION (TA ONLY) WITH
AVEC ASSERTED, USE VECTORS 25 TO 31,
DEPANDING ON INTERRUPT LEVEL
2) IF NORMAL TERMINATION (TA ONLY) WITH
AVEC NEGATED, USE VECTOR GIVEN IN
D7–D0
3) IF BUS ERROR TERMINATION, USE VEC-
TOR 24
4) IF RETRY TERMINATION, RETRY IACK
CYCLE
1) NEGATE TIP OR START NEXT CYCLE 1) THREE-STATE D31–D0
2) NEGATE AVEC IF NECESSARY
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