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List of Illustrations
MOTOROLA
M68060 USER’S MANUAL
xxi
7-38 Line Read Access Bus Cycle Terminated with TEA Timing............................. 7-49
7-39 Retry Read Bus Cycle Timing .......................................................................... 7-50
7-40 Line Write Retry Bus Cycle Timing................................................................... 7-51
7-41 MC68040-Arbitration Protocol State Diagram .................................................. 7-57
7-42 MC68060-Arbitration Protocol State Diagram .................................................. 7-64
7-43 Processor Bus Request Timing........................................................................ 7-67
7-44 Arbitration During Relinquish and Retry Timing ............................................... 7-68
7-45 Implicit Bus Ownership Arbitration Timing........................................................ 7-69
7-46 Effect of BGR on Locked Sequences............................................................... 7-70
7-47 Snooped Bus Cycle.......................................................................................... 7-71
7-48 Initial Power-On Reset Timing.......................................................................... 7-72
7-49 Normal Reset Timing........................................................................................ 7-73
7-50 Data Bus Usage During Reset ......................................................................... 7-74
7-51 Acknowledge Termination Ignore State Example ............................................ 7-75
7-52 Extra Data Write Hold Example........................................................................ 7-77
8-1 General Exception Processing Flowchart .......................................................... 8-2
8-2 General Form of Exception Stack Frame ........................................................... 8-3
8-3 Interrupt Recognition Examples ....................................................................... 8-13
8-4 Interrupt Exception Processing Flowchart........................................................ 8-15
8-5 Reset Exception Processing Flowchart............................................................ 8-16
8-6 Fault Status Long-Word Format ....................................................................... 8-22
9-1 JTAG Test Logic Block Diagram ........................................................................ 9-3
9-2 JTAG Idcode Register Format............................................................................ 9-7
9-3 Output Pin Cell (O.Pin)....................................................................................... 9-8
9-4 Observe-Only Input Pin Cell (I.Obs)................................................................... 9-8
9-5 Input Pin Cell (I.Pin) ........................................................................................... 9-9
9-6 Output Control Cell (IO.Ctl) ................................................................................ 9-9
9-7 General Arrangement of Bidirectional Pin Cells ............................................... 9-10
9-8 JTAG Bypass Register ..................................................................................... 9-15
9-9 Circuit Disabling IEEE Standard 1149.1........................................................... 9-16
9-10 Debug Command Interface Schematic ............................................................ 9-25
9-11 Interface Timing................................................................................................ 9-26
9-12 Transition from JTAG to Debug Mode Timing Diagram ................................... 9-34
9-13 Transition from Debug to JTAG Mode Timing Diagram ................................... 9-35
11-1 Linear Voltage Regulator Solution.................................................................... 11-7
11-2 LTC1147 Voltage Regulator Solution............................................................... 11-8
11-3 LTC1148 Voltage Regulator Solution............................................................... 11-9
11-4 MAX767 Voltage Regulator Solution.............................................................. 11-10
11-5 MC68040 Address Hold Time ........................................................................ 11-11
11-6 MC68060 Address Hold Time ........................................................................ 11-12
11-7 MC68060 Address Hold Time Fix .................................................................. 11-12
11-8 Simple CLK Generation.................................................................................. 11-14
11-9 Generic CLK Generation ................................................................................ 11-14
11-10 MC68040 BCLK to CLKEN Relationship........................................................11-15
11-11 DRAM Timing Analysis................................................................................... 11-15
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