Loading...
Bus Operation
MOTOROLA M68060 USER’S MANUAL 7-33
and debounce these signals. An interrupt request that is held constant for two consecutive
CLK periods is considered a valid input. Although the protocol requires that the request
remain until the processor runs an interrupt acknowledge cycle for that interrupt value, an
interrupt request that is held for as short a period as two CLK cycles can be potentially rec-
ognized. Figure 7-25 is a flowchart of the procedure for a pending interrupt condition.
The MC68060 asserts IPEND when an interrupt request is pending. Figure 7-26 illustrates
the assertion of IPEND relative to the assertion of an interrupt level on the IPLx signals.
IPEND signals external devices that an interrupt exception will be taken at an upcoming
Figure 7-24. Using CLA in a High-Speed DRAM Design
Figure 7-25. Interrupt Pending Procedure
TS
TA
RAS
CAS
A3–A2
DRAM ADDRESS
CLA
ROW C0 C1 C2 C3 C0
CLK
DATA
(WRITE CYCLE)
DATA
(READ CYCLE)
W0 W1 W2 W3 W0
RESET
SAMPLE AND SYNCHRONIZE
IPL2–IPL0
ASSERT IPEND
OTHERWISE
INTERRUPT LEVEL I2–I0,
OR TRANSITION ON LEVEL 7
>
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com