Bus Operation
BUSCR is used to control the LOCK and LOCKE outputs. Refer to 7.4 Bus Control Regis-
ter for the format of the BUSCR. Emulation of these instructions is done as part of the
MC68060 software package (M68060SP). Refer to Appendix C MC68060 Software Pack-
age for more information.
7.7.7 Using CLA to Increment A3 and A2
The MC68060 provides the capability to cycle long-word address bits A3, A2 based on the
CLA signal, which should assist in supporting high-speed DRAM systems. CLA may also be
used to support bursting for slaves which do not burst.
The processor begins sampling CLA immediately following the BCLK rising edge that
causes TS to assert. The initial address of the line transfer is that of the first requested or
needed long word and the attributes are those of the line transfer. After each BCLK rising
edge when CLA is asserted, the long-word address (A3, A2) increments in circular wrap-
around fashion. If CLA is negated, A3, A2 does not change, but remains fixed, as on the
MC68040 processor. Since CLA is not an acknowledge termination signal, it is not affected
by the acknowledge termination ignore state capability, if that mode is enabled. Also note
that the A3, A2 increments in a circular wrap around fashion for as many times as CLA is
asserted about a rising BCLK edge.
Figure 7-24 shows how CLA may be used for a high-speed DRAM design. In this figure, the
DRAM design requires a means of cycling A3, A2 before TA is asserted to the processor.
CLA provides a method of avoiding a delay which would otherwise be incurred with the use
of an external medium-scale integration (MSI) counter. W0 to W3 represent A3, A2 incre-
menting. C0 to C3 represent the column address sequencing caused by the change of A3,
A2. The timing diagram represents a 5:3:3:3 design, which is feasible with a full-speed 50-
MHz clock and 65-ns page-mode DRAMs.
Bus transfers with transfer type signals TT1 and TT0 = $3 are classified as acknowledge bus
cycles. The following paragraphs describe interrupt acknowledge, breakpoint acknowledge,
and LPSTOP broadcast bus cycles that use this encoding.
7.8.1 Interrupt Acknowledge Cycles
When a peripheral device requires the services of the MC68060 or is ready to send informa-
tion that the processor requires, it can signal the processor to take an interrupt exception.
The interrupt exception transfers control to a routine that responds appropriately. The
peripheral device uses the interrupt priority level signals (IPLx) to signal an interrupt condi-
tion to the processor and to specify the priority level for the condition. Refer to Section 8
Exception Processing for a discussion on the IPLx levels and IPEND.
The status register (SR) of the MC68060 contains an interrupt priority mask (I2–I0 bits). The
value in the interrupt mask is the highest priority level that the processor ignores. When an
interrupt request has a priority higher than the value in the mask, the processor makes the
request a pending interrupt. IPLx must maintain the interrupt request level until the
MC68060 acknowledges the interrupt to guarantee that the interrupt is recognized. The
MC68060 continuously samples IPLx on consecutive rising edges of CLK to synchronize
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