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Bus Operation
7-30 M68060 USER’S MANUAL MOTOROLA
recognized asserted, the processor ignores the data and appends a wait state instead of
terminating the transfer. The processor continues to sample TA on successive rising edg-
es of BCLK until TA is recognized as asserted. The registered data is then passed to the
appropriate memory unit. If more than one read cycle is required to read in the operand(s),
C1 and C2 are repeated accordingly.
Figure 7-23. Locked Bus Cycle for TAS Instruction Timing
C1 C2 CI C3 C4
LOCKE
LOCK
LOCKED TRANSFER
BCLK
SIZ1–SIZ0
MISCELLANEOUS
ATTRIBUTES
TS
TIP
TA
R/W
BS3–BS0
CIOUT
SAS
LONG
PRE
DRIVE
D31–D0
A1–A0
A31–A2
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.
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