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Bus Operation
7-28 M68060 USER’S MANUAL MOTOROLA
sertion and terminates the line write bus cycle, TIP remains asserted if the processor is
ready to begin another bus cycle. Otherwise, the processor negates TIP during the next
clock. The processor also three-states the data bus during the next clock following termi-
nation of the write cycle.
7.7.5 Locked Read-Modify-Write Cycles
The locked read-modify-write sequence performs a read, conditionally modifies the data in
the processor, and writes the data out to memory. In the MC68060, this operation can be
indivisible, providing semaphore capabilities for multiprocessor systems. During the entire
Figure 7-22. Line Write Bus Cycle Timing
BCLK
SIZ1–SIZ0
MISCELLANEOUS
ATTRIBUTES
TS
TIP
TA
R/W
BS3–BS0
C1 C2 C3 C4 C5
TBI
CIOUT
CLA
10 11 0001
SAS
PRE
DRIVE
D31–D0
A1–A0
A3–A2
A31–A4
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.
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