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Bus Operation
MOTOROLA M68060 USER’S MANUAL 7-27
states are generated, a burst-inhibited line write completes in eight clocks instead of the
five required for a burst write.
Clock 3 (C3)
The processor drives the second long word of data on the data bus and holds the address
and transfer attribute signals constant during C3. The selected device either increments
A3 and A2 to reference the next long word, or requests the processor to increment A3 and
A2 via the CLA input.
The selected device then registers this data from the data bus and asserts TA. At the end
of C3, assuming the acknowledge termination ignore state capability is disabled, the pro-
cessor samples the level of TA; if TA is asserted, the transfer terminates.
If TA is not recognized asserted at the end of C3, the processor inserts wait states instead
of terminating the transfer. The processor continues to sample TA on successive rising
edges of BCLK until TA is recognized asserted.
Clock 4 (C4)
This clock is identical to C3 except that the value driven on the data bus corresponds to
the third long word of data for the burst.
Clock 5 (C5)
This clock is identical to C3 except that the value driven on the data bus corresponds to
the fourth long word of data for the burst. After the processor recognizes the last TA as-
Figure 7-21. Line Write Burst-Inhibited Cycle Flowchart
1) INCREMENT A3–A2
2) DRIVE SIZ1–SIZ0 TO LONG
3) ASSERT TS FOR ONE BCLK
4) ASSERT SAS IMMEDIATELY IF
ACKNOWLEDGE TERMINATION IGNORE
STATE CAPABILITY DISABLED. ELSE,
ASSERT SAS AFTER WRITE PRIMARY
IGNORE STATE COUNTER HAS EXPIRED
5) PLACE DATA ON D31–D0
1) DECODE ADDRESS
2) REGISTER DATA FROM D31–D0
3) ASSERT TA FOR ONE BCLK
4) NEGATE CLA
1) THREE-STATE D31–D0
2) NEGATE LOCK, LOCKE IF NECESSARY
1) NEGATE TIP OR START NEXT CYCLE
CONTINUED FROM FIGURE 7-20
4 LW NOT DONE
4 LW DONE
PROCESSOR SYSTEM
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