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List of Illustrations
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M68060 USER’S MANUAL
MOTOROLA
6-4 Floating-Point Condition Code (FPSR) .............................................................. 6-5
6-5 Floating-Point Quotient Byte (FPSR) ................................................................. 6-5
6-6 Floating-Point Exception Status Byte (FPSR).................................................... 6-6
6-7 Floating-Point Accrued Exception Byte (FPSR)................................................. 6-6
6-8 Intermediate Result Format.............................................................................. 6-12
6-9 Rounding Algorithm Flowchart ......................................................................... 6-14
6-10 Floating-Point State Frame .............................................................................. 6-35
6-11 Status Word Contents ...................................................................................... 6-36
7-1 Signal Relationships to Clocks........................................................................... 7-2
7-2 Full-Speed Clock................................................................................................ 7-2
7-3 Half-Speed Clock ............................................................................................... 7-2
7-4 Quarter-Speed Clock ......................................................................................... 7-3
7-5 Bus Control Register Format.............................................................................. 7-4
7-6 Internal Operand Representation....................................................................... 7-5
7-7 Data Multiplexing................................................................................................ 7-6
7-8 Byte Select Signal Generation and PAL Equation ............................................. 7-8
7-9 Example of a Misaligned Long-Word Transfer................................................. 7-10
7-10 Example of Misaligned Word Transfer ............................................................. 7-10
7-11 Misaligned Long-Word Read Bus Cycle Timing............................................... 7-11
7-12 Byte, Word, and Long-Word Read Cycle Flowchart ........................................ 7-13
7-13 Byte, Word, and Long-Word Read Bus Cycle Timing ...................................... 7-14
7-14 Line Read Cycle Flowchart .............................................................................. 7-17
7-15 Line Read Transfer Timing............................................................................... 7-18
7-16 Burst-Inhibited Line Read Cycle Flowchart ...................................................... 7-20
7-17 Burst-Inhibited Line Read Bus Cycle Timing.................................................... 7-21
7-18 Byte, Word, and Long-Word Write Transfer Flowchart .................................... 7-22
7-19 Long-Word Write Bus Cycle Timing ................................................................. 7-23
7-20 Line Write Cycle Flowchart .............................................................................. 7-26
7-21 Line Write Burst-Inhibited Cycle Flowchart ...................................................... 7-27
7-22 Line Write Bus Cycle Timing ............................................................................ 7-28
7-23 Locked Bus Cycle for TAS Instruction Timing.................................................. 7-30
7-24 Using CLA in a High-Speed DRAM Design ..................................................... 7-33
7-25 Interrupt Pending Procedure ............................................................................ 7-33
7-26 Assertion of IPEND .......................................................................................... 7-34
7-27 Interrupt Acknowledge Cycle Flowchart........................................................... 7-36
7-28 Interrupt Acknowledge Bus Cycle Timing ........................................................ 7-37
7-29 Autovector Interrupt Acknowledge Bus Cycle Timing ...................................... 7-38
7-30 Breakpoint Interrupt Acknowledge Cycle Flowchart......................................... 7-39
7-31 Breakpoint Interrupt Acknowledge Bus Cycle Timing ...................................... 7-40
7-32 LPSTOP Broadcast Cycle Flowchart ............................................................... 7-41
7-33 LPSTOP Broadcast Bus Cycle Timing, BG Negated ....................................... 7-42
7-34 LPSTOP Broadcast Bus Cycle Timing, BG Asserted ...................................... 7-43
7-35 Exiting LPSTOP Mode Flowchart..................................................................... 7-44
7-36 Exiting LPSTOP Mode Timing Diagram........................................................... 7-45
7-37 Word Write Access Bus Cycle Terminated with TEA Timing ........................... 7-48
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