Bus Operation
Clock 1 (C1)
The write cycle starts in C1. During C1, the processor places valid values on the address
bus and transfer attributes. The processor asserts TS during C1 to indicate the beginning
of a bus cycle. If not already asserted from a previous bus cycle, the TIP signal is also
asserted at this time to indicate that a bus cycle is active.
The processor pre-conditions the data bus during C1 to improve AC timing. The process
of pre-conditioning involves reinforcing the logic level that is already at the data pin. If the
voltage level is originally zero volts, nothing is done; if the voltage level is 3.3 V, that volt-
age level is reinforced; however, if the voltage level is originally 5 V, the processor drives
that data pin from 5 V down to 3.3 V. Note that no active logic change is done at this time.
The actual logic level change is done in C2. This pre-conditioning affects operation prima-
rily when using the processor in a 5-V system.
For user and supervisor mode accesses, which the corresponding memory unit trans-
lates, the UPAx signals are driven with the values from the U1 and U0 bits for the area.
The TTx and TMx signals identify the specific access type. The R/W signal is driven low
for a write cycle. CIOUT is asserted if the access is identified as noncachable or if the ac-
cess references an alternate address space. Refer to Section 4 Memory Management
Unit for information on the MC68060 and MC68LC060 memory units and Appendix B
MC68EC060 for information on the MC68EC060 memory unit.
Clock 2 (C2)
During C2, the processor negates TS and drives the appropriate bytes of the data bus with
the data to be written. All other bytes are driven with undefined values. The selected de-
vice uses R/W, SIZ1, SIZ0, A1, A0, or BS3–BS0, and CIOUT to register only the required
information from the data bus. With the exception of R/W and CIOUT, these signals also
select any or all of the bytes (D31–D24, D23–D16, D15–D8, and D7–D0). If C2 is not a
wait state (CW), then the selected peripheral device asserts the TA signal.
The MC68060 implements a special mode called the acknowledge termination ignore
state capability to aid in high-frequency designs. In this mode, the processor begins the
sampling of termination signals such as TA after a user-programmed number of BCLK ris-
ing edges has expired. The SAS signal is provided as a status output to indicate which
BCLK rising edge the processor begins to sample the termination signals. If this mode is
disabled, SAS is asserted during C2 to indicate that the processor immediately begins
sampling the terminations signals. Refer to 7.14.1 Acknowledge Termination Ignore
State Capability for details on this special mode.
Assuming that the acknowledge termination ignore state capability is disabled, at the end
of the C2, the processor samples the level of TA, terminating the bus cycle if TA is assert-
ed. If TA is not recognized asserted at the end of the clock cycle, the processor ignores
the data and inserts a wait state instead of terminating the transfer. The processor contin-
ues to sample TA on successive rising edges of BCLK until TA is recognized asserted.
The data bus then three-states and the bus cycle ends.
When the processor recognizes TA at the rising BCLK edge and terminates the bus cycle,
TIP remains asserted if the processor is ready to begin another bus cycle. Otherwise, the
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