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Bus Operation
7-20 M68060 USER’S MANUAL MOTOROLA
7.7.3 Byte, Word, and Long-Word Write Cycles
During a write transfer, the processor transfers data to a memory or peripheral device. The
level on the TCI signal is ignored by the processor during all write cycles. The bus controller
performs byte, word, and long-word write transfers for the following cases:
Accesses to a disabled cache
Accesses to a memory page that is specified noncachable
Accesses that are implicitly noncachable (locked read-modify-write accesses, access-
es to an alternate logical address space via the MOVES instruction, and table searches)
Writes to writethrough pages
Accesses that do not allocate in the data cache on a write miss (exception stacking)
The first transfer of a line write is terminated with TBI, forcing completion of the line ac-
cess using three additional long-word write transfers
Cache line pushes for lines containing a single dirty long word.
Figure 7-18 and Figure 7-19 illustrate a flowchart and functional timing diagram for byte,
word, and long-word write bus transfers.
Figure 7-16. Burst-Inhibited Line Read Cycle Flowchart
1) INCREMENT A3–A2
2) DRIVE SIZ1–SIZ0 TO LONG
3) ASSERT TS FOR ONE BCLK
4) ASSERT SAS IMMEDIATELY IF
ACKNOWLEDGE TERMINATION IGNORE
STATE CAPABILITY DISABLED. ELSE,
ASSERT SAS AFTER READ PRIMARY
IGNORE STATE COUNTER HAS EXPIRED 1) DECODE ADDRESS
2) PLACE DATA ON D31–D0
3) ASSERT TA FOR ONE BCLK
4) NEGATE CLA
1) REGISTER DATA
1) NEGATE LOCK, LOCKE IF NECESSARY
1) NEGATE TIP OR START NEXT CYCLE 1) THREE-STATE D31–D0
CONTINUED FROM FIGURE 7-14
4 LW NOT DONE
4 LW DONE
PROCESSOR SYSTEM
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