Bus Operation
asserted. The registered data and the value of TCI are then passed to the appropriate
memory unit.
If TBI was negated with the assertion of TA, the processor continues the cycle with C3.
Otherwise, if TBI was asserted, the line transfer is burst inhibited, and the processor reads
the remaining three long words using long-word read bus cycles. The processor incre-
ments A3 and A2 for each read, and the new address is placed on the address bus for
each bus cycle. Refer to 7.7.1 Byte, Word, and Long-Word Read Transfer Cycles for
information on long-word reads. If no wait states are generated, a burst-inhibited line read
completes in eight clocks instead of the five required for a burst read.
Clock 3 (C3)
The processor holds the address and transfer attribute signals constant during C3 if CLA
is negated. The selected device must either increment A3 and A2 to reference the next
long word to transfer, place the data on the data bus, and assert TA, or alteratively assert
the CLA input to request the processor to increment A3 and A2. Refer to 7.7.7 Using CLA
to Increment A3 and A2 for details on CLA operation.
As in the description of C2, using acknowledge termination ignore state capability, the pro-
cessor ignores any termination signal, such as TA, until a user-programmable number of
BCLK edges has expired. And, as in the description in C2, SAS indicates the first BCLK
rising edge in which acknowledge termination signals become significant. If this mode is
disabled, SAS stays asserted in C3 to indicate that the processor will sample TA immedi-
ately. Refer to 7.14.1 Acknowledge Termination Ignore State Capability for details on
this mode.
Assuming that the acknowledge termination ignore state capability is disabled, the pro-
cessor samples the level of TA and registers the current value on the data bus at the end
of C3. If TA is asserted, the transfer terminates and the second long word of data is
passed to the appropriate memory unit. If TA is not recognized asserted at the end of C3,
the processor ignores the latched data and inserts wait states instead of terminating the
transfer. The processor continues to sample TA on successive rising edges of BCLK until
it is recognized asserted. The registered data is then passed to the appropriate memory
Clock 4 (C4)
This clock is identical to C3 except that once TA is recognized asserted, the registered
value corresponds to the third long word of data for the burst.
Clock 5 (C5)
This clock is identical to C3 except that once TA is recognized, the registered value cor-
responds to the fourth long word of data for the burst. After the processor recognizes the
last TA assertion and terminates the line read bus cycle, TIP remains asserted if the pro-
cessor is ready to begin another bus cycle. Otherwise, the processor negates TIP during
the next clock.
Figure 7-16 and Figure 7-17 illustrate a flowchart and functional timing diagram for a
burst-inhibited line read bus cycle.
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