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Bus Operation
7-18
M68060 USER’S MANUAL
MOTOROLA
abled, SAS is asserted during C2 to indicate that the processor immediately begins sam-
pling the terminations signals. Refer to
7.14.1 Acknowledge Termination Ignore State
Capability
for details on this special mode.
Assuming that the acknowledge termination ignore state capability is disabled, the pro-
cessor samples the level of TA, TBI, and TCI and registers the current value on the data
bus at the end of C2. If TA is asserted, the transfer terminates and the data is passed to
the appropriate memory unit. If TA is not recognized asserted, the processor ignores the
data and inserts wait states instead of terminating the transfer. The processor continues
to sample TA, TBI, and TCI on successive rising edges of BCLK until TA is recognized
Figure 7-15. Line Read Transfer Timing
BCLK
MISCELLANEOUS
ATTRIBUTES
TS
TIP
TA
R/W
BS3–BS0
C1 C2 C3 C4 C5
TBI
CIOUT
CLA
A3–A2 10 11 0001
SAS
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.
SIZ1–SIZ0
D31–D0
A31–A4
A1–A0
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