Bus Operation
cycles, the bus controller still treats the four transfers as a single line bus cycle and does not
allow other unrelated processor accesses or bus arbitration to intervene between the trans-
fers. TBI is ignored after the first long-word transfer.
Line reads to support cache line filling can be cache inhibited by asserting transfer cache
inhibit (TCI) with TA for the first long-word transfer of the line. The assertion of TCI does not
affect completion of the line transfer, but the bus controller registers and passes it to the
memory controller for use. TCI is ignored after the first long-word transfer of a line burst bus
cycle and during the three long-word bus cycles of a burst-inhibited line transfer.
The address placed on the address bus by the processor for line bus cycle does not neces-
sarily point to the most significant byte of each long word because A1 and A0 are copied
from the original operand address supplied to the memory unit by the integer unit for line
reads. These two bits are also unchanged for the three long-word bus cycles of a burst-
inhibited line transfer. The selected device should ignore A1 and A0 for long-word and line
read transfers.
The address of an instruction fetch will always be aligned to a long-word boundary
($xxxxxxx0, $xxxxxxx4, $xxxxxxx8, or $xxxxxxxC). This is unlike the MC68040 in which the
prefetches occur on half-line boundaries. Therefore, compilers should attempt to locate
branch targets on long-word boundaries to minimize branch stalls. For example, if the target
of a branch is an instruction that starts at $1000000E, the following burst sequence will occur
upon a cache miss: $1000000C, $10000000, $10000004, then $10000008. Figure 7-14 and
Figure 7-15 illustrate a flowchart and functional timing diagram for a line read bus transfer.
Clock 1 (C1)
The line read cycle starts in C1. During C1, the processor places valid values on the ad-
dress bus and transfer attributes. For user and supervisor mode accesses that are trans-
lated by the corresponding memory unit, the UPAx signals are driven with the values from
the matching U1 and U0 bits. The TTx and TMx signals identify the specific access type.
The R/W signal is driven high for a read cycle, and the size signals (SIZx) indicate line
size. CIOUT is asserted for a MOVE16 operand read if the access is identified as non-
cachable. Refer to
Section 4 Memory Management Unit
for information on the
MC68060 and MC68LC060 memory units and
Appendix B MC68EC060
for information
on the MC68EC060 memory unit.
The processor asserts TS during C1 to indicate the beginning of a bus cycle. If not already
asserted from a previous bus cycle, TIP is also asserted at this time to indicate that a bus
cycle is active.
Clock 2 (C2)
During C2, the processor negates TS. The selected device uses R/W and SIZx to place
the data on the data bus. (The first transfer must supply the long word at the correspond-
ing long-word boundary.) Concurrently, the selected device asserts TA and either negates
TBI to indicate it can or asserts TBI to indicate it cannot support a burst transfer.
The MC68060 implements a special mode called the acknowledge termination ignore
state capability to aid in high-frequency designs. In this mode, the processor begins sam-
pling termination signals such as TA after a user-programmed number of BCLK rising
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