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MOTOROLA
M68060 USER’S MANUAL
xix
LIST OF ILLUSTRATIONS
1-1 MC68060 Block Diagram ................................................................................... 1-6
1-2 Programming Model ......................................................................................... 1-12
2-1 Functional Signal Groups ................................................................................... 2-3
3-1 MC68060 Integer Unit Pipeline .......................................................................... 3-1
3-2 Integer Unit User Programming Model............................................................... 3-2
3-3 Integer Unit Supervisor Programming Model ..................................................... 3-3
3-4 Status Register................................................................................................... 3-4
3-5 Processor Configuration Register ...................................................................... 3-5
4-1 Memory Management Unit ................................................................................. 4-2
4-2 Memory Management Programming Model ....................................................... 4-3
4-3 URP and SRP Register Formats........................................................................ 4-3
4-4 Translation Control Register Format .................................................................. 4-4
4-5 Transparent Translation Register Format .......................................................... 4-6
4-6 Translation Table Structure ................................................................................ 4-8
4-7 Logical Address Format ..................................................................................... 4-8
4-8 Detailed Flowchart of Table Search Operation ................................................ 4-10
4-9 Detailed Flowchart of Descriptor Fetch Operation ........................................... 4-11
4-10 Table Descriptor Formats................................................................................. 4-12
4-11 Page Descriptor Formats ................................................................................. 4-12
4-12 Example Translation Table............................................................................... 4-15
4-13 Translation Table Using Indirect Descriptors ................................................... 4-16
4-14 Translation Table Using Shared Tables ........................................................... 4-18
4-15 Translation Table with Nonresident Tables ...................................................... 4-19
4-16 Translation Table Structure for Two Tasks ...................................................... 4-21
4-17 Logical Address Map with Shared Supervisor and User Address Spaces....... 4-22
4-18 Translation Table Using S-Bit and W-Bit To Set Protection ............................. 4-23
4-19 ATC Organization............................................................................................. 4-24
4-20 ATC Entry and Tag Fields ................................................................................ 4-25
4-21 Address Translation Flowchart......................................................................... 4-29
5-1 MC68060 Instruction and Data Caches ............................................................. 5-2
5-2 Instruction Cache Line Format ........................................................................... 5-2
5-3 Data Cache Line Format .................................................................................... 5-2
5-4 Caching Operation ............................................................................................. 5-3
5-5 Cache Control Register ...................................................................................... 5-5
5-6 Instruction Cache Line State Diagram.............................................................. 5-16
5-7 Data Cache Line State Diagrams..................................................................... 5-18
6-1 Floating-Point Unit Block Diagram ..................................................................... 6-2
6-2 Floating-Point User Programming Model ........................................................... 6-3
6-3 Floating-Point Control Register Format.............................................................. 6-4
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