M68060 USER’S MANUAL
The processor asserts transfer start (TS) during C1 to indicate the beginning of a bus cy-
cle. If not already asserted from a previous bus cycle, the transfer in progress (TIP) signal
is also asserted at this time to indicate that a bus cycle is active.
Figure 7-13. Byte, Word, and Long-Word Read Bus Cycle Timing
BYTE READ WORD READ
C1 CW C1 C2C2
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.