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Bus Operation
7-14
M68060 USER’S MANUAL
MOTOROLA
The processor asserts transfer start (TS) during C1 to indicate the beginning of a bus cy-
cle. If not already asserted from a previous bus cycle, the transfer in progress (TIP) signal
is also asserted at this time to indicate that a bus cycle is active.
Figure 7-13. Byte, Word, and Long-Word Read Bus Cycle Timing
C1 C2
BCLK
BYTE
TS
TIP
TA
R/W
120
LONG
BYTE READ WORD READ
WITH WAIT
LONG-WORD
READ
C1 CW C1 C2C2
WORD
BS0
BS1
BS2
BS3
ADDRESS AND
ATTRIBUTES
SAS
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.
SIZ1–SIZ0
D31–D24
A1–A0
D23–D16
D15–D8
D7–D0
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