Bus Operation
bus cycle. The MC68060 system designer and programmer should account for these
effects, particularly in time-critical applications.
The transfer of data between the processor and other devices involves the address bus,
data bus, and control and attribute signals. The address and data buses are normally par-
allel, nonmultiplexed buses, supporting byte, word, long-word, and line (16-byte) bus cycles.
Line transfers are normally performed using an efficient burst transfer, which provides an
initial address and time-multiplexes the data bus to transfer four long words of information
to or from the slave device. Slave devices that do not support bursting can burst-inhibit the
first long word of a line transfer, forcing the bus master to complete the access using three
additional long-word bus cycles. All bus input and output signals are synchronized with
respect to the rising edge of the BCLK signal. The MC68060 moves data on the bus by issu-
ing control signals and using a handshake protocol to ensure correct data movement. The
following paragraphs describe the bus cycles for byte, word, long-word, and line read, write,
and read-modify-write transfers.
In general, the bus cycle protocol supported by the MC68060 processor is similar to that
supported by the MC68040 processor. In addition to the basic MC68060 protocol, there are
special modes that can be selected during reset by selectively setting the IPLx and data bus
D15–D0. For the purpose of simplifying the description of the MC68060 bus, this sub-sec-
7.7 Processor Data Transfers
, describes the behavior of the MC68060 processor
assuming that none of the special modes are selected during reset. For the description of
the MC68060 bus cycle protocol when the special modes are enabled, refer to
7.14 Special
Modes of Operation
7.7.1 Byte, Word, and Long-Word Read Transfer Cycles
During a read transfer, the processor receives data from a memory or peripheral device.
Since the data read for a byte, word, or long-word access is not placed in either of the inter-
nal caches by definition, the processor ignores the transfer cache inhibit (TCI) signal when
registering the data. The bus controller performs byte, word, and long-word read transfers
for the following cases:
Accesses to a disabled cache
Accesses to a memory page that is specified noncachable
Accesses that are implicitly noncachable (locked read-modify-write accesses, access-
es to an alternate logical address space via the MOVES instruction, and table searches)
Table 7-3. Memory Alignment Influence on
Noncachable and Writethrough Bus Cycles
Transfer Size Number of Bus Cycles
$0* $1* $2* $3*
Instruction 1 N/A N/A N/A
Byte Operand 1 1 1 1
Word Operand 1 2 1 2
Long-Word Operand 1 3 2 3
*Where the byte offset (A1 and A0) equals this encoding.
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