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Bus Operation
MOTOROLA
M68060 USER’S MANUAL
7-11
The combination of operand size and alignment determines the number of bus cycles
required to perform a particular memory access. Table 7-3 lists the number of bus cycles
required for different operand sizes with all possible alignment conditions for read and write
cycles. The table confirms that alignment significantly affects bus cycle throughput for non-
cachable accesses. For example, in Figure 7-9 the misaligned long-word operand took three
bus cycles because the byte offset = $1. If the byte offset = $0, then it would have taken one
Figure 7-11. Misaligned Long-Word Read Bus Cycle Timing
A31–A2
BCLK
SIZ1–SIZ0
D31–D24
TS
TIP
TA
A1–A0
D23–D16
D15–D8
D7–D0
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE
READ
WORD
READ
BYTE
READ
R/W
C1 C2 C1 C2 C1 C2
BYTE WORD BYTE
120
MISCELLANEOUS
ATTRIBUTES
BS0
BS1
BS2
BS3
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